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| M58WR064HU M58WR064HL 64 Mbit (4Mb x16, Mux I/O, Multiple Bank, Burst) 1.8V supply Flash memories Feature summary Supply voltage -VDD = 1.7V to 2V for Program, Erase and Read - VDDQ = 1.7V to 2V for I/O Buffers - VPP = 12V for fast Program (9V tolerant) Multiplexed address/data Synchronous / asynchronous read - Synchronous Burst Read mode: 66MHz - Random Access: 70ns Synchronous burst read suspend Programming time - 8s by Word typical for Fast Factory Program - Double/Quadruple Word Program option - Enhanced Factory Program options Memory blocks - Multiple Bank Memory Array: 4 Mbit Banks - Parameter Blocks (Top or Bottom location) Dual operations - Program Erase in one Bank while Read in others - No delay between Read and Write operations Block locking - All blocks locked at Power up - Any combination of blocks can be locked - WP for Block Lock-Down Security - 128 bit user programmable OTP cells - 64 bit unique device number Common Flash Interface (CFI) 100,000 program/erase cycles per block FBGA VFBGA44 7.7 x 9mm (ZB) 7.5 x 5mm (ZA) Electronic signature - Manufacturer Code: 20h - Top Device Code, M58WR064HU: 88C0h - Bottom Device Code, M58WR064HL: 88C1h Package - ECOPACK(R) November 2007 Rev 5 1/114 www.numonyx.com 1 Contents M58WR064HU M58WR064HL Contents 1 2 Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 2.11 2.12 2.13 2.14 2.15 2.16 Address Inputs (ADQ0-ADQ15, A16-A21) . . . . . . . . . . . . . . . . . . . . . . . . 13 Data Input/Output (ADQ0-ADQ15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Chip Enable (E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Output Enable (G) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Write Enable (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Write Protect (WP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Reset/Power-Down (RP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Latch Enable (L) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Clock (K) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Wait (WAIT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Bus Invert (BINV) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 VDD Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 VDDQ Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 VPP Program Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 VSS Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 VSSQ Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3 Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.1 3.2 3.3 3.4 3.5 3.6 Bus Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Bus Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Address Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Output Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Reset/Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4 5 Command interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Command interface - Standard commands . . . . . . . . . . . . . . . . . . . . . 19 5.1 Read Array command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2/114 M58WR064HU M58WR064HL Contents 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 5.10 5.11 5.12 5.13 5.14 Read Status Register command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Read Electronic Signature command . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Read CFI Query command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Clear Status Register command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Block Erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Program/Erase Suspend command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Program/Erase Resume command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Protection Register Program command . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Set Configuration Register command . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Block Lock command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Block Unlock command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Block Lock-Down command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6 Command interface - Factory program commands . . . . . . . . . . . . . . . 27 6.0.1 Bank Erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.1 6.2 6.3 Double Word Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Quadruple Word Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Enhanced Factory Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6.3.1 6.3.2 6.3.3 6.3.4 Setup Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Program Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Verify Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Exit Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.4 Quadruple Enhanced Factory Program command . . . . . . . . . . . . . . . . . . 32 6.4.1 6.4.2 6.4.3 6.4.4 Setup Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Load Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Program and Verify Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Exit Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 7 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7.0.1 7.0.2 7.0.3 7.0.4 7.0.5 Program/Erase Controller Status Bit (SR7) . . . . . . . . . . . . . . . . . . . . . . 35 Erase Suspend Status Bit (SR6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Erase Status Bit (SR5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Program Status Bit (SR4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 VPP Status Bit (SR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3/114 Contents 7.0.6 7.0.7 7.0.8 M58WR064HU M58WR064HL Program Suspend Status Bit (SR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Block Protection Status Bit (SR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Bank Write/Multiple Word Program Status Bit (SR0) . . . . . . . . . . . . . . . 37 8 Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8 8.9 8.10 8.11 Read Select Bit (CR15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Bus Invert Configuration (CR14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 X-Latency Bits (CR13-CR11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Wait Polarity Bit (CR10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Data Output Configuration Bit (CR9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Wait Configuration Bit (CR8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Burst Type Bit (CR7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Valid Clock Edge Bit (CR6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Power-Down Bit (CR5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Wrap Burst Bit (CR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Burst length Bits (CR2-CR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 9 Read modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 9.1 9.2 9.3 Asynchronous Read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Synchronous Burst Read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 9.2.1 Synchronous Burst Read Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Single Synchronous Read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 10 11 Dual operations and multiple bank architecture . . . . . . . . . . . . . . . . . 50 Block locking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 11.1 11.2 11.3 11.4 11.5 Reading a block's lock status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Locked state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Unlocked state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Lock-Down state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Locking operations during Erase Suspend . . . . . . . . . . . . . . . . . . . . . . . . 53 12 13 Program and erase times and endurance cycles . . . . . . . . . . . . . . . . . 55 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 4/114 M58WR064HU M58WR064HL Contents 14 15 16 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Appendix A Block address tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Appendix B Common Flash Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Appendix C Flowcharts and pseudo codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 16.1 16.2 Enhanced factory program pseudo code . . . . . . . . . . . . . . . . . . . . . . . . 106 Quadruple Enhanced Factory Program pseudo code . . . . . . . . . . . . . . 108 Appendix D Command interface state tables. . . . . . . . . . . . . . . . . . . . . . . . . . . 109 17 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 5/114 List of tables M58WR064HU M58WR064HL List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Bank architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Command codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Standard commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Electronic Signature Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Factory Program commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Status Register bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 X-Latency Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Burst type definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Dual operations allowed in other banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Dual operations allowed in same bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Dual operation limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Lock status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Program, erase times and endurance cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 DC Characteristics - Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 DC characteristics - voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Asynchronous read AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Synchronous read AC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Write AC characteristics, Write Enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Write AC characteristics, Chip Enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Reset and Power-up AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 VFBGA44 - 7.7x9mm, 10x4 ball array, 0.5mm pitch package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 VFBGA44 7.5 x 5mm - 10x4 ball array - 0.50mm pitch, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Top boot block addresses, M58WR064HU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Bottom boot block addresses, M58WR064HL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Query structure overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 CFI Query Identification String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 CFI Query system interface information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Device geometry definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Primary algorithm-specific extended query table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Protection Register information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Burst read information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Bank and erase block region information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Bank and erase block region 1 information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Bank and erase block region 2 information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Command interface states - modify table, next state . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Command interface states - modify table, next output . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Command interface states - lock table, next state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Command interface states - lock table, next output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 6/114 M58WR064HU M58WR064HL List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 VFBGA connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Protection Register memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 X-latency and data output configuration example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Wait configuration example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 AC measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Asynchronous random access read AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Synchronous burst read AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Single synchronous read AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Synchronous burst read suspend AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Clock input AC Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Write AC waveforms, Write Enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Write AC waveforms, Chip Enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Reset and Power-up AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 VFBGA44 - 7.7x9mm, 10x4 ball array, 0.5mm pitch, Bottom View Package Outline . . . . . 72 VFBGA44 7.5 x 5mm - 10x4 ball array - 0.50mm pitch, package outline. . . . . . . . . . . . . . 74 VFBGA44 Daisy Chain - Package Connections (Top view through package) . . . . . . . . . . 76 VFBGA44 Daisy Chain - PCB connection proposal (top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Program flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Double Word Program flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Quadruple Word Program flowchart and pseudo code. . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Program Suspend & Resume flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . . . 100 Block Erase flowchart and pseudo code. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Erase Suspend & Resume flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Locking Operations flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Protection Register Program flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . . . 104 Enhanced Factory Program flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Quadruple Enhanced Factory Program flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 7/114 Summary description M58WR064HU M58WR064HL 1 Summary description The M58WR064HU/L are 64 Mbit (4 Mbit x16) non-volatile Flash memories. They may be erased electrically at block level and programmed in-system on a Word-by-Word basis using a 1.7V to 2V VDD supply for the circuitry and a 1.7V to 2V VDDQ supply for the Input/Output pins. An optional 12V (9V tolerant) VPP power supply is provided to speed up customer programming. The first sixteen address lines are multiplexed with the Data Input/Output signals on the multiplexed address/data bus ADQ0-ADQ15. The remaining address lines A16-A21 are the Most Significant Bit addresses. The device features an asymmetrical block architecture. The M58WR064HU and M58WR064HL have an array of 135 blocks, and are divided into 4 Mbit banks. There are 15 banks each containing 8 main blocks of 32 KWords, and one parameter bank containing 8 parameter blocks of 4 KWords and 7 main blocks of 32 KWords. The Multiple Bank Architecture allows Dual Operations, while programming or erasing in one bank, Read operations are possible in other banks. Only one bank at a time is allowed to be in Program or Erase mode. It is possible to perform burst reads that cross bank boundaries. The bank architecture is summarized in Table 2, and the memory maps are shown in Figure 3 The Parameter Blocks are located at the top of the memory address space for the M58WR064HU, and at the bottom for the M58WR064HL. Each block can be erased separately. Erase can be suspended, in order to perform program in any other block, and then resumed. Program can be suspended to read data in any other block and then resumed. Each block can be programmed and erased over 100,000 cycles using the supply voltage VDD. There are two Enhanced Factory programming commands available to speed up programming. Program and Erase commands are written to the Command Interface of the memory. An internal Program/Erase Controller takes care of the timings necessary for program and erase operations. The end of a program or erase operation can be detected and any error conditions identified in the Status Register. The command set required to control the memory is consistent with JEDEC standards. The device supports synchronous burst read and asynchronous read from all blocks of the memory array; at power-up the device is configured for asynchronous read. In synchronous burst mode, data is output on each clock cycle at frequencies of up to 66MHz. The synchronous burst read operation can be suspended and resumed. The device features an Automatic Standby mode. When the bus is inactive during Asynchronous Read operations, the device automatically switches to the Automatic Standby mode. In this condition the power consumption is reduced to the standby value IDD4 and the outputs are still driven. The M58WR064HU/L feature an instant, individual block locking scheme that allows any block to be locked or unlocked with no latency, enabling instant code and data protection. All blocks have three levels of protection. They can be locked and locked-down individually preventing any accidental programming or erasure. There is an additional hardware protection against program and erase. When VPP VPPLK all blocks are protected against program or erase. All blocks are locked at Power- Up. 8/114 M58WR064HU M58WR064HL Summary description The device includes a Protection Register to increase the protection of a system's design. The Protection Register is divided into two segments: a 64 bit segment containing a unique device number written by Numonyx, and a 128 bit segment One-Time-Programmable (OTP) by the user. The user programmable segment can be permanently protected. Figure 4, shows the Protection Register Memory Map. The M58WR064HU/L is available in VFBGA44, 7.7 x 9mm and VFBGA44 7.5 x 5, 10x4 active ball array, 0.5mm pitch packages. The memories are supplied with all the bits erased (set to '1'). Figure 1. Logic diagram VDD VDDQ VPP 16 A16-A21 W E G RP WP L K M58WR064HU M58WR064HL BINV ADQ0-ADQ15 WAIT VSS VSSQ AI10557c 9/114 Summary description Table 1. A16-A21 ADQ0-ADQ15 E G W RP WP K L WAIT BINV VDD VDDQ VPP VSS VSSQ NC M58WR064HU M58WR064HL Signal names Address Inputs Data Input/Outputs or Address Inputs, Command Inputs Chip Enable Output Enable Write Enable Reset/Power-down Write Protect Clock Latch Enable Wait Bus Invert Supply Voltage Supply Voltage for Input/Output Buffers Optional Supply Voltage for Fast Program & Erase Ground Ground Input/Output Supply Not Connected Internally 10/114 Figure 2. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 M58WR064HU M58WR064HL A NC NC B C WAIT VSS A19 A21 K VDD W VPP A17 NC D VDDQ A16 A20 L BINV RP WP A18 E VSSQ E VSS ADQ7 ADQ6 ADQ13 ADQ3 ADQ12 ADQ2 ADQ9 ADQ8 G VFBGA connections (top view through package) F ADQ15 ADQ14 VSSQ ADQ5 ADQ4 ADQ11 ADQ10 VDDQ ADQ1 ADQ0 G H NC NC Summary description 11/114 AI12018b Summary description Table 2. Bank architecture Bank Size 4 Mbit 4 Mbit 4 Mbit 4 Mbit ---- M58WR064HU M58WR064HL Number Parameter Bank Bank 1 Bank 2 Bank 3 ---- Parameter Blocks 8 blocks of 4 KWord ---- Main Blocks 7 blocks of 32 KWord 8 blocks of 32 KWord 8 blocks of 32 KWord 8 blocks of 32 KWord ---8 blocks of 32 KWord 8 blocks of 32 KWord Bank 14 Bank 15 4 Mbit 4 Mbit - Figure 3. Memory map M58WR064HU - Top Boot Block Address lines A21-A16 and ADQ15-ADQ0 000000h 007FFFh 32 KWord 8 Main Blocks 32 KWord Parameter Bank M58WR064HL - Bottom Boot Block Address lines A21-A16 and ADQ15-ADQ0 000000h 000FFFh 007000h 007FFFh 008000h 00FFFFh 038000h 03FFFFh 040000h 047FFFh Bank 1 078000h 07FFFFh 080000h 087FFFh Bank 2 0B8000h 0BFFFFh 0C0000h 0C7FFFh Bank 3 0F8000h 0FFFFFh 7 Main Blocks 32 KWord 4 KWord 8 Parameter Blocks Bank 15 4 KWord 3C0000h 3C7FFFh 3F8000h 3FFFFFh 32 KWord 8 Main Blocks 32 KWord AI10568 4 KWord 8 Parameter Blocks 4KWord 32 KWord 7 Main Blocks 32 KWord 32 KWord 8 Main Blocks 32 KWord 32 KWord 8 Main Blocks 32 KWord 32 KWord 8 Main Blocks 32 KWord Bank 15 038000h 03FFFFh 300000h 307FFFh Bank 3 338000h 33FFFFh 340000h 347FFFh Bank 2 378000h 37FFFFh 380000h 387FFFh Bank 1 3B8000h 3BFFFFh 3C0000h 3C7FFFh 3F0000h 3F7FFFh 3F8000h 3F8FFFh 3FF000h 3FFFFFh 32 KWord 8 Main Blocks 32 KWord 32 KWord 8 Main Blocks 32 KWord 32 KWord 8 Main Blocks 32 KWord 32 KWord Parameter Bank 12/114 M58WR064HU M58WR064HL Signal descriptions 2 Signal descriptions See Figure 1: Logic diagram and Table 1: Signal names, for a brief overview of the signals connected to this device. 2.1 Address Inputs (ADQ0-ADQ15, A16-A21) The Address Inputs select the cells in the memory array to access during Bus Read operations. During Bus Write operations they control the commands sent to the Command Interface of the Program/Erase Controller. 2.2 Data Input/Output (ADQ0-ADQ15) The Data I/O outputs the data stored at the selected address during a Bus Read operation or inputs a command or the data to be programmed during a Bus Write operation. 2.3 Chip Enable (E) The Chip Enable input activates the memory control logic, input buffers, decoders and sense amplifiers. When Chip Enable is at VILand Reset is at VIH the device is in active mode. When Chip Enable is at VIH the memory is deselected, the outputs are high impedance and the power consumption is reduced to the stand-by level. 2.4 Output Enable (G) The Output Enable controls data outputs during the Bus Read operation of the memory. 2.5 Write Enable (W) The Write Enable controls the Bus Write operation of the memory's Command Interface. The data is latched on the rising edge of Chip Enable or Write Enable whichever occurs first. 2.6 Write Protect (WP) Write Protect is an input that gives an additional hardware protection for each block. When Write Protect is at VIL, the Lock-Down is enabled and the protection status of the LockedDown blocks cannot be changed. When Write Protect is at VIH, the Lock-Down is disabled and the Locked-Down blocks can be locked or unlocked. (refer to Table 15: Lock status). 13/114 Signal descriptions M58WR064HU M58WR064HL 2.7 Reset/Power-Down (RP) The Reset/Power-Down input provides a hardware reset of the memory, and/or power-down functions, depending on the settings in the Configuration Register. When Reset/PowerDown is at VIL, the memory is in reset mode: the outputs are high impedance and the current consumption is reduced to the Standby Supply Current IDD3, or to the Reset/PowerDown Supply Current IDD2 if the Power-Down function is enabled. Refer to Table 20: DC Characteristics - Currents, for the value of IDD2 and IDD3. After reset all blocks are in the Locked state and the bits of the Configuration Register are reset except for Power-Down bit CR5. When Reset/Power-Down is at VIH, the device is in normal operation. Exiting reset mode the device enters Asynchronous Read mode, but a negative transition of Chip Enable or Latch Enable is required to ensure valid data outputs. The Reset pin can be interfaced with 3V logic without any additional circuitry. It can be tied to VRPH (refer to Table 21: DC characteristics - voltages). 2.8 Latch Enable (L) Latch Enable latches the ADQ0-ADQ15 and A16-A21 address bits on its rising edge. The address latch is transparent when Latch Enable is at VIL and it is inhibited when Latch Enable is at VIH. 2.9 Clock (K) The clock input synchronizes the memory to the microcontroller during synchronous read operations; the address is latched on a Clock edge (rising or falling, according to the configuration settings) when Latch Enable is at VIL. Clock is don't care during asynchronous read and in write operations. 2.10 Wait (WAIT) Wait is an output signal used during synchronous read to indicate whether the data on the output bus are valid. This output is high impedance when Chip Enable is at VIH or Reset is at VIL. It can be configured to be active during the wait cycle or one clock cycle in advance. The WAIT signal is forced deasserted when Output Enable is at VIH. 2.11 Bus Invert (BINV) Bus invert is an input/output signal used to reduce the amount of power required to switch the external address/data bus. Power is saved by inverting the data on ADQ0-ADQ15 each time the inversion results in a reduced number of pin transitions. Data is inverted when BINV is at VIH (i.e. if the data is AAAAh and BINV is at VIH, AAAAh becomes 5555h). BINV is high impedance when Chip Enable or Output Enable is at VIH or when Reset/Power Down is at VIL. 14/114 M58WR064HU M58WR064HL Signal descriptions 2.12 VDD Supply Voltage VDD provides the power supply to the internal core of the memory device. It is the main power supply for all operations (Read, Program and Erase). 2.13 VDDQ Supply Voltage VDDQ provides the power supply to the I/O pins and enables all Outputs to be powered independently from VDD. VDDQ can be tied to VDD or can use a separate supply. 2.14 VPP Program Supply Voltage VPP is both a control input and a power supply pin. The two functions are selected by the voltage range applied to the pin. If VPP is kept in a low voltage range (0V to VDDQ) VPP is seen as a control input. In this case a voltage lower than VPPLK gives an absolute protection against program or erase, while VPP in the VPP1 range enables these functions (see Tables 20 and 21, DC Characteristics for the relevant values). VPP is only sampled at the beginning of a program or erase; a change in its value after the operation has started does not have any effect and program or erase operations continue. If VPP is in the range of VPPH it acts as a power supply pin. In this condition VPP must be stable until the Program/Erase algorithm is completed. 2.15 VSS Ground VSS ground is the reference for the core supply. It must be connected to the system ground. 2.16 VSSQ Ground VSSQ ground is the reference for the input/output circuitry driven by VDDQ. VSSQ must be connected to VSS. Note: Each device in a system should have VDD, VDDQ and VPP decoupled with a 0.1F ceramic capacitor close to the pin (high frequency, inherently low inductance capacitors should be as close as possible to the package). See Figure 8: AC measurement load circuit. The PCB track widths should be sufficient to carry the required VPP program and erase currents. 15/114 Bus operations M58WR064HU M58WR064HL 3 Bus operations There are six standard bus operations that control the device. These are Bus Read, Bus Write, Address Latch, Output Disable, Standby and Reset. See Table 3: Bus operations, for a summary. Typically glitches of less than 5ns on Chip Enable or Write Enable are ignored by the memory and do not affect Bus Write operations. 3.1 Bus Read Bus Read operations are used to output the contents of the Memory Array, the Electronic Signature, the Status Register and the Common Flash Interface. Both Chip Enable and Output Enable must be at VIL in order to perform a read operation. The Chip Enable input should be used to enable the device. Output Enable should be used to gate data onto the output. The data read depends on the previous command written to the memory (see Section 4: Command interface). See Figures 9, 10 and 11 Read AC Waveforms, and Tables 22 and 23 Read AC Characteristics, for details of when the output becomes valid. 3.2 Bus Write Bus Write operations write Commands to the memory or latch Input Data to be programmed. A bus write operation is initiated when Chip Enable and Write Enable are at VIL with Output Enable at VIH. Commands and Input Data are latched on the rising edge of Write Enable or Chip Enable, whichever occurs first. The addresses must also be latched prior to the write operation by toggling Latch Enable (when Chip Enable is at VIL). The Latch Enable must be tied to VIH during the bus write operation. See Figures 14 and 15, Write AC Waveforms, and Tables 24 and 25, Write AC Characteristics, for details of the timing requirements. 3.3 Address Latch Address latch operations input valid addresses. Both Chip enable and Latch Enable must be at VIL during address latch operations. The addresses are latched on the rising edge of Latch Enable. 3.4 Output Disable The outputs are high impedance when the Output Enable is at VIH. 16/114 M58WR064HU M58WR064HL Bus operations 3.5 Standby Standby disables most of the internal circuitry allowing a substantial reduction of the current consumption. The memory is in stand-by when Chip Enable and Reset are at VIH. The power consumption is reduced to the stand-by level and the outputs are set to high impedance, independently from the Output Enable or Write Enable inputs. If Chip Enable switches to VIH during a program or erase operation, the device enters Standby mode when finished. 3.6 Reset/Power-Down During reset mode the memory is deselected and the outputs are high impedance. The memory is in reset mode when Reset/Power-Down is at VIL. The power consumption is reduced to the Standby level, or to the Reset/Power-Down level if the Power-Down function is enabled, independently of the Chip Enable, Output Enable or Write Enable inputs. If Reset/Power-Down is pulled to VSS during a Program or Erase, this operation is aborted and the memory content is no longer valid. Table 3. Bus operations E VIL VIL VIL VIL VIH x G VIL VIH VIH VIH x x W VIH VIL x VIH x x L VIH VIH VIL VIH x x RP VIH VIH VIH VIH VIH VIL Hi-Z Hi-Z WAIT(2) ADQ15-ADQ0 Data Output Data Input Address Input Hi-Z Hi-Z Hi-Z Operation(1) Bus Read Bus Write Address Latch Output Disable Standby Reset/Power-Down 1. x = Don't care. 2. WAIT signal polarity is configured using the Set Configuration Register command. 17/114 Command interface M58WR064HU M58WR064HL 4 Command interface All Bus Write operations to the memory are interpreted by the Command Interface. Commands consist of one or more sequential Bus Write operations. An internal Program/Erase Controller handles all timings and verifies the correct execution of the Program and Erase commands. The Program/Erase Controller provides a Status Register whose output may be read at any time to monitor the progress or the result of the operation. The Command Interface is reset to read mode when power is first applied, when exiting from Reset or whenever VDD is lower than VLKO. Command sequences must be followed exactly. Any invalid combination of commands will reset the device to read mode. Refer to Table 4: Command codes, and Appendix D, Tables 42, 43, 44 and 45, Command Interface States - Modify and Lock Tables, for a summary of the Command Interface. The Command Interface is split into two types of commands: Standard commands and Factory Program commands. The following sections explain in detail how to perform each command. Table 4. Command codes Command Block Lock Confirm Set Configuration Register Confirm Alternative Program Setup Block Erase Setup Block Lock-Down Confirm Enhanced Factory Program Setup Double Word Program Setup Program Setup Clear Status Register Quadruple Word Program Setup Block Lock Setup, Block Unlock Setup, Block Lock Down Setup and Set Configuration Register Setup Read Status Register Quadruple Enhanced Factory Program Setup Bank Erase Setup Read Electronic Signature Read CFI Query Program/Erase Suspend Protection Register Program Program/Erase Resume, Block Erase Confirm, Bank Erase Confirm, Block Unlock Confirm or Enhanced Factory Program Confirm Read Array Hex Code 01h 03h 10h 20h 2Fh 30h 35h 40h 50h 56h 60h 70h 75h 80h 90h 98h B0h C0h D0h FFh 18/114 M58WR064HU M58WR064HL Command interface - Standard commands 5 Command interface - Standard commands The following commands are the basic commands used to read, write to and configure the device. Refer to Table 5: Standard commands, in conjunction with the following text descriptions. 5.1 Read Array command The Read Array command returns the addressed bank to Read Array mode. One Bus Write cycle is required to issue the Read Array command and return the addressed bank to Read Array mode. Subsequent read operations will read the addressed location and output the data. A Read Array command can be issued in one bank while programming or erasing in another bank. However if a Read Array command is issued to a bank currently executing a Program or Erase operation the command will be executed but the output data is not guaranteed. 5.2 Read Status Register command The Status Register indicates when a Program or Erase operation is complete and the success or failure of operation itself. Issue a Read Status Register command to read the Status Register content. The Read Status Register command can be issued at any time, even during Program or Erase operations. The following read operations output the content of the Status Register of the addressed bank. The Status Register is latched on the falling edge of E or G signals, and can be read until E or G returns to VIH. Either E or G must be toggled to update the latched data. See Table 8 for the description of the Status Register Bits. This mode supports asynchronous or single synchronous reads only. 5.3 Read Electronic Signature command The Read Electronic Signature command reads the Manufacturer and Device Codes, the Block Locking Status, the Protection Register, and the Configuration Register. The Read Electronic Signature command consists of one write cycle to an address within one of the banks. A subsequent Read operation in the same bank will output the Manufacturer Code, the Device Code, the protection Status of the blocks in the targeted bank, the Protection Register, or the Configuration Register (see Table 6). Dual operations between the Parameter bank and the Electronic Signature location are not allowed (see Table 14: Dual operation limitations). If a Read Electronic Signature command is issued in a bank that is executing a Program or Erase operation the bank will go into Read Electronic Signature mode, subsequent Bus Read cycles will output the Electronic Signature data and the Program/Erase controller will continue to program or erase in the background. This mode supports asynchronous or single synchronous reads only, it does not support synchronous burst reads. 19/114 Command interface - Standard commands M58WR064HU M58WR064HL 5.4 Read CFI Query command The Read CFI Query command is used to read data from the Common Flash Interface (CFI). The Read CFI Query Command consists of one Bus Write cycle, to an address within one of the banks. Once the command is issued subsequent Bus Read operations in the same bank read from the Common Flash Interface. If a Read CFI Query command is issued in a bank that is executing a Program or Erase operation the bank will go into Read CFI Query mode, subsequent Bus Read cycles will output the CFI data and the Program/Erase controller will continue to Program or Erase in the background. This mode supports asynchronous or single synchronous reads only, it does not support synchronous burst reads. The status of the other banks is not affected by the command (see Table 12). After issuing a Read CFI Query command, a Read Array command should be issued to the addressed bank to return the bank to Read Array mode. Dual operations between the Parameter Bank and the CFI memory space are not allowed (see Table 14: Dual operation limitations). See Appendix B: Common Flash Interface, Tables 32, 33, 34, 35, 36, 37, 38, 39, 40 and 41 for details on the information contained in the Common Flash Interface memory area. 5.5 Clear Status Register command The Clear Status Register command can be used to reset (set to `0') error bits SR1, SR3, SR4 and SR5 in the Status Register. One bus write cycle is required to issue the Clear Status Register command. After the Clear Status Register command the bank returns to read mode. The error bits in the Status Register do not automatically return to `0' when a new command is issued. The error bits in the Status Register should be cleared before attempting a new Program or Erase command. 20/114 M58WR064HU M58WR064HL Command interface - Standard commands 5.6 Block Erase command The Block Erase command can be used to erase a block. It sets all the bits within the selected block to '1'. All previous data in the block is lost. If the block is protected then the Erase operation will abort, the data in the block will not be changed and the Status Register will output the error. The Block Erase command can be issued at any moment, regardless of whether the block has been programmed or not. Two Bus Write cycles are required to issue the command. The first bus cycle sets up the Erase command. The second latches the block address to the Program/Erase Controller and starts it. If the second bus cycle is not Write Erase Confirm (D0h), Status Register bits SR4 and SR5 are set and the command aborts. Erase aborts if Reset turns to VIL. As data integrity cannot be guaranteed when the Erase operation is aborted, the block must be erased again. Once the command is issued the device outputs the Status Register data when any address within the bank is read. At the end of the operation the bank will remain in Read Status Register mode until a Read Array, Read CFI Query or Read Electronic Signature command is issued. During Erase operations the bank containing the block being erased will only accept the Read Array, Read Status Register, Read Electronic Signature, Read CFI Query and the Program/Erase Suspend command, all other commands will be ignored. Refer to Section 10: Dual operations and multiple bank architecture for detailed information about simultaneous operations allowed in banks not being erased. Typical Erase times are given in Table 16: Program, erase times and endurance cycles. See Appendix C, Figure 25: Block Erase flowchart and pseudo code, for a suggested flowchart for using the Block Erase command. 5.7 Program command The memory array can be programmed word-by-word. Only one Word in one bank can be programmed at any one time. If the block being programmed is protected then the Program operation will abort, the data in the block will not be changed and the Status Register will output the error. Two bus write cycles are required to issue the Program Command. The first bus cycle sets up the Program command. The second latches the Address and the Data to be written and starts the Program/Erase Controller. After programming has started, read operations in the bank being programmed output the Status Register content. During Program operations the bank being programmed will only accept the Read Array, Read Status Register, Read Electronic Signature, Read CFI Query and the Program/Erase Suspend command. Refer to Section 10: Dual operations and multiple bank architecture for detailed information about simultaneous operations allowed in banks not being programmed. Typical Program times are given in Table 16: Program, erase times and endurance cycles. Programming aborts if Reset goes to VIL. As data integrity cannot be guaranteed when the program operation is aborted, the memory location must be reprogrammed. See Appendix C, Figure 21: Program flowchart and pseudo code, for the flowchart for using the Program command. 21/114 Command interface - Standard commands M58WR064HU M58WR064HL 5.8 Program/Erase Suspend command The Program/Erase Suspend command is used to pause a Program or Block Erase operation. A Bank Erase operation cannot be suspended. One bus write cycle is required to issue the Program/Erase command. Once the Program/Erase Controller has paused bits SR7, SR6 and/ or SR2 of the Status Register will be set to `1'. The command can be addressed to any bank. During Program/Erase Suspend the Command Interface will accept the Program/Erase Resume, Read Array (cannot read the suspended block), Read Status Register, Read Electronic Signature and Read CFI Query commands. Additionally, if the suspend operation was Erase then the Clear status Register, Program, Block Lock, Block Lock-Down or Block Unlock commands will also be accepted. The block being erased may be protected by issuing the Block Lock, Block Lock-Down or Protection Register Program commands. Only the blocks not being erased may be read or programmed correctly. When the Program/Erase Resume command is issued the operation will complete. Refer to the Section 10: Dual operations and multiple bank architecture for detailed information about simultaneous operations allowed during Program/Erase Suspend. During a Program/Erase Suspend, the device can be placed in standby mode by taking Chip Enable to VIH. Program/Erase is aborted if Reset turns to VIL. See Appendix C, Figure 24: Program Suspend & Resume flowchart and pseudo code, and Figure 26: Erase Suspend & Resume flowchart and pseudo code, for flowcharts for using the Program/Erase Suspend command. 5.9 Program/Erase Resume command The Program/Erase Resume command can be used to restart the Program/Erase Controller after a Program/Erase Suspend command has paused it. One Bus Write cycle is required to issue the command. The command can be written to any address. The Program/Erase Resume command does not change the read mode of the banks. If the suspended bank was in Read Status Register, Read Electronic signature or Read CFI Query mode the bank remains in that mode and outputs the corresponding data. If the bank was in Read Array mode subsequent read operations will output invalid data. If a Program command is issued during a Block Erase Suspend, then the erase cannot be resumed until the programming operation has completed. It is possible to accumulate suspend operations. For example: suspend an erase operation, start a programming operation, suspend the programming operation then read the array. See Appendix C, Figure 24: Program Suspend & Resume flowchart and pseudo code, and Figure 26: Erase Suspend & Resume flowchart and pseudo code, for flowcharts for using the Program/Erase Resume command. 22/114 M58WR064HU M58WR064HL Command interface - Standard commands 5.10 Protection Register Program command The Protection Register Program command is used to Program the 128 bit user One-TimeProgrammable (OTP) segment of the Protection Register and the Protection Register Lock. The segment is programmed 16 bits at a time. When shipped all bits in the segment are set to `1'. The user can only program the bits to `0'. Two write cycles are required to issue the Protection Register Program command. The first bus cycle sets up the Protection Register Program command. The second latches the Address and the Data to be written to the Protection Register and starts the Program/Erase Controller. Read operations output the Status Register content after the programming has started. The segment can be protected by programming bit 1 of the Protection Lock Register (see Figure 4: Protection Register memory map). Attempting to program a previously protected Protection Register will result in a Status Register error. The protection of the Protection Register is not reversible. The Protection Register Program cannot be suspended. Dual operations between the Parameter B ank and the Protection Register memory space are not allowed (see Table 14: Dual operation limitations). See Appendix C, Figure 28: Protection Register Program flowchart and pseudo code, for a flowchart for using the Protection Register Program command. 5.11 Set Configuration Register command The Set Configuration Register command is used to write a new value to the Configuration Register which defines the burst length, type, X latency, Synchronous/Asynchronous Read mode and the valid Clock edge configuration. Two Bus Write cycles are required to issue the Set Configuration Register command. The first cycle writes the setup command and the address corresponding to the Configuration Register content. The second cycle writes the Configuration Register data and the confirm command. Once the command is issued the memory returns to Read mode. The values of the Configuration Register must always be presented on ADQ15-ADQ0. CR0 is on ADQ0, CR1 on ADQ1, etc.; the other address bits are ignored. 23/114 Command interface - Standard commands M58WR064HU M58WR064HL 5.12 Block Lock command The Block Lock command is used to lock a block and prevent Program or Erase operations from changing the data in it. All blocks are locked at power-up or reset. Two Bus Write cycles are required to issue the Block Lock command. The first bus cycle sets up the Block Lock command. The second Bus Write cycle latches the block address. The lock status can be monitored for each block using the Read Electronic Signature command. Table 15 shows the Lock Status after issuing a Block Lock command. The Block Lock bits are volatile, once set they remain set until a hardware reset or powerdown/power-up. They are cleared by a Block Unlock command. Refer to Section 11: Block locking, for a detailed explanation. See Appendix C, Figure 27: Locking Operations flowchart and pseudo code, for a flowchart for using the Lock command. 5.13 Block Unlock command The Block Unlock command is used to unlock a block, allowing the block to be programmed or erased. Two Bus Write cycles are required to issue the Block Unlock command. The first bus cycle sets up the Block Unlock command. The second Bus Write cycle latches the block address. The lock status can be monitored for each block using the Read Electronic Signature command. Table 15 shows the protection status after issuing a Block Unlock command. Refer to Section 11: Block locking, for a detailed explanation and Appendix C, Figure 27: Locking Operations flowchart and pseudo code, for a flowchart for using the Unlock command. 5.14 Block Lock-Down command A locked or unlocked block can be locked-down by issuing the Block Lock-Down command. A locked-down block cannot be programmed or erased, or have its protection status changed when WP is low, VIL. When WP is high, VIH, the Lock-Down function is disabled and the locked blocks can be individually unlocked by the Block Unlock command. Two Bus Write cycles are required to issue the Block Lock-Down command. The first bus cycle sets up the Block Lock command. The second Bus Write cycle latches the block address. The lock status can be monitored for each block using the Read Electronic Signature command. Locked-Down blocks revert to the locked (and not locked-down) state when the device is reset on power-down. Table 15 shows the Lock Status after issuing a Block LockDown command. Refer to Section 11: Block locking, for a detailed explanation and Appendix C, Figure 27: Locking Operations flowchart and pseudo code, for a flowchart for using the Lock-Down command. 24/114 M58WR064HU M58WR064HL Table 5. Standard commands Command interface - Standard commands Bus Operations(1) Commands Cycles 1st Cycle Op. Read Array Read Status Register Read Electronic Signature Read CFI Query Clear Status Register Block Erase Program Program/Erase Suspend Program/Erase Resume Protection Register Program Set Configuration Register Block Lock Block Unlock Block Lock-Down 1+ 1+ 1+ 1+ 1 2 2 1 1 2 2 2 2 2 Write Write Write Write Write Write Write Write Write Write Write Write Write Write Add BKA BKA BKA BKA X BKA or BA(3) BKA or X X PRA CRD BKA or BA BKA or BA BKA or (3) (3) 2nd Cycle Data FFh 70h 90h 98h 50h 20h 40h or 10h B0h D0h C0h 60h 60h 60h 60h Write Write Write Write Write PRA CRD BA BA BA PRD 03h 01h D0h 2Fh Write Write BA WA D0h PD Op. Read Read Read Read Add WA BKA(2) BKA (2) Data RD SRD ESD QD BKA(2) WA(3) BA(3) 1. X = Don't Care, WA=Word Address in targeted bank, RD = Read Data, SRD = Status Register Data, ESD = Electronic Signature Data, QD = Query Data, BA = Block Address, BKA = Bank Address, PD = Program Data, PRA = Protection Register Address, PRD = Protection Register Data, CRD = Configuration Register Data. 2. Must be same bank as in the first cycle. The signature addresses are listed in Table 6. 3. Any address within the bank can be used. 25/114 Command interface - Standard commands Table 6. Electronic Signature Codes Code Manufacturer Code Top (M58WR064HU) Device Code Bottom (M58WR064HL) Locked Unlocked Block Protection Locked and Locked-Down Unlocked and Locked-Down Die Revision Code Configuration Register Numonyx Factory Default Protection Register Lock OTP Area Permanently Locked M58WR064HU M58WR064HL Address (h) Bank Address + 00 Bank Address + 01 Bank Address + 01 Data (h) 0020 88C0 88C1 0001 0000 Block Address + 02 0003 0002 Bank Address + 03 Bank Address + 05 Bank Address + 80 0000 Bank Address + 81 Bank Address + 84 Unique Device Number OTP Area DRC(1) CR(2) 0002 Protection Register Bank Address + 85 Bank Address + 8C 1. DRC = Die Revision Code. 2. CR = Configuration Register. Figure 4. Protection Register memory map PROTECTION REGISTER 8Ch User Programmable OTP 85h 84h Unique device number 81h 80h Protection Register Lock 1 0 AI08149 26/114 M58WR064HU M58WR064HL Command interface - Factory program commands 6 Command interface - Factory program commands The Factory Program commands are used to speed up programming. They require VPP to be at VPPH. Refer to Table 7: Factory Program commands, in conjunction with the following text descriptions. 6.0.1 Bank Erase command The Bank Erase command can be used to erase a bank. It sets all the bits within the selected bank to '1'. All previous data in the bank is lost. The Bank Erase command will ignore any protected blocks within the bank. If all blocks in the bank are protected then the Bank Erase operation will abort and the data in the bank will not be changed. The Status Register will not output any error. Bank Erase operations can be performed at both VPP = VPPH and V PP = VDD Two Bus Write cycles are required to issue the command. The first bus cycle sets up the Bank Erase command. The second latches the bank address in the Program/Erase Controller and starts it. If the second bus cycle is not Write Bank Erase Confirm (D0h), Status Register bits SR4 and SR5 are set and the command aborts. Erase aborts if Reset turns to VIL. As data integrity cannot be guaranteed when the Erase operation is aborted, the bank must be erased again. Once the command is issued the device outputs the Status Register data when any address within the bank is read. At the end of the operation the bank will remain in Read Status Register mode until a Read Array, Read CFI Query or Read Electronic Signature command is issued. During Bank Erase operations the bank being erased will only accept the Read Array, Read Status Register, Read Electronic Signature and Read CFI Query command, all other commands will be ignored. A Bank Erase operation cannot be suspended. Dual Operations are not supported during Bank Erase operations and the command cannot be suspended. Typical Erase times are given in Table 16: Program, erase times and endurance cycles 27/114 Command interface - Factory program commands M58WR064HU M58WR064HL 6.1 Double Word Program command The Double Word Program command improves the programming throughput by writing a page of two adjacent words in parallel. The two words must differ only for the address ADQ0. If the block being programmed is protected then the Program operation will abort, the data in theblock will not be changed and the Status Register will output the error. VPP must be set to VPPH during the Double Word Program, otherwise the command will be ignored and the Status register will not output any errors Three bus write cycles are necessary to issue the Double Word Program command. The first bus cycle sets up the Double Word Program Command. The second bus cycle latches the Address and the Data of the first word to be written. The third bus cycle latches the Address and the Data of the second word to be written and starts the Program/Erase Controller. Read operations in the bank being programmed output the Status Register content after the programming has started. During Double Word Program operations the bank being programmed will only accept the Read Array, Read Status Register, Read Electronic Signature and Read CFI Query command, all other commands will be ignored. Dual operations are not supported during Double Word Program operations and the command cannot be suspended. Typical Program times are given in Table 16: Program, erase times and endurance cycles. Programming aborts if Reset goes to VIL. As data integrity cannot be guaranteed when the program operation is aborted, the memory locations must be reprogrammed. See Appendix C, Figure 22: Double Word Program flowchart and pseudo code, for the flowchart for using the Double Word Program command. 28/114 M58WR064HU M58WR064HL Command interface - Factory program commands 6.2 Quadruple Word Program command The Quadruple Word Program command improves the programming throughput by writing a page of four adjacent words in parallel. The four words must differ only for the addresses ADQ0 and ADQ1. VPP must be set to VPPH during the Quadruple Word Program, otherwise the command will be ignored and the Status register will not output any errors. If the block being programmed is protected then the Program operation will abort, the data in the block will not be changed and the Status Register will output the error. Five bus write cycles are necessary to issue the Quadruple Word Program command. The first bus cycle sets up the Double Word Program Command. The second bus cycle latches the Address and the Data of the first word to be written. The third bus cycle latches the Address and the Data of the second word to be written. The fourth bus cycle latches the Address and the Data of the third word to be written. The fifth bus cycle latches the Address and the Data of the fourth word to be written and starts the Program/Erase Controller. Read operations to the bank being programmed output the Status Register content after the programming has started. Programming aborts if Reset goes to VIL. As data integrity cannot be guaranteed when the program operation is aborted, the memory locations must be reprogrammed. During Quadruple Word Program operations the bank being programmed will only accept the Read Array, Read Status Register, Read Electronic Signature and Read CFI Query command, all other commands will be ignored. Dual operations are not supported during Quadruple Word Program operations and the command cannot be suspended. Typical Program times are given in Table 16: Program, erase times and endurance cycles. See Appendix C, Figure 23: Quadruple Word Program flowchart and pseudo code, for the flowchart for using the Quadruple Word Program command. 29/114 Command interface - Factory program commands M58WR064HU M58WR064HL 6.3 Enhanced Factory Program command The Enhanced Factory Program command can be used to program large streams of data within any one block. It greatly reduces the total programming time when a large number of Words are written to a block at any one time. If the block being programmed is protected then the Program operation will abort, the data in the block will not be changed and the Status Register will output the error. The use of the Enhanced Factory Program command requires certain operating conditions. VPP must be set to VPPH VDD must be within operating range Ambient temperature TA must be 30C 10C The targeted block must be unlocked Dual operations are not supported during the Enhanced Factory Program operation and the command cannot be suspended. For optimum performance the Enhanced Factory Program commands should be limited to a maximum of 100 program/erase cycles per block. If this limit is exceeded the internal algorithm will continue to work properly but some degradation in performance is possible. Typical Program times are given in Table 16. The Enhanced Factory Program command has four phases: the Setup Phase, the Program Phase to program the data to the memory, the Verify Phase to check that the data has been correctly programmed and reprogram if necessary and the Exit Phase. Refer to Table 7: Factory Program commands, and Figure 29: Enhanced Factory Program flowchart. 6.3.1 Setup Phase The Enhanced Factory Program command requires two Bus Write operations to initiate the command. The first bus cycle sets up the Enhanced Factory Program command. The second bus cycle confirms the command. The Status Register P/E.C. Bit SR7 should be read to check that the P/E.C. is ready. After the confirm command is issued, read operations output the Status Register data. The read Status Register command must not be issued as it will be interpreted as data to program. If the second bus cycle is not EFP confirm(D0h), the Status Register bits SR4 and SR5 are set and the command will be aborted. VPP value must be in the VPPH range during the Confirm command, otherwise SR4 and SR3 will be set and the command will be aborted. 30/114 M58WR064HU M58WR064HL Command interface - Factory program commands 6.3.2 Program Phase The Program Phase requires n+1 cycles, where n is the number of Words (refer to Table 7: Factory Program commands and Figure 29: Enhanced Factory Program flowchart). Three successive steps are required to issue and execute the Program Phase of the command. 1. Use one Bus Write operation to latch the Start Address and the first Word to be programmed. The Status Register Bank Write Status bit SR0 should be read to check that the P/E.C. is ready for the next Word. Each subsequent Word to be programmed is latched with a new Bus Write operation. The address can either remain the Start Address, in which case the P/E.C. increments the address location or the address can be incremented in which case the P/E.C. jumps to the new address. If any address that is not in the same block as the Start Address is given with data FFFFh, the Program Phase terminates and the Verify Phase begins. The Status Register bit SR0 should be read between each Bus Write cycle to check that the P/E.C. is ready for the next Word. Finally, after all Words have been programmed, write one Bus Write operation with data FFFFh to any address outside the block containing the Start Address, to terminate the programming phase. If the data is not FFFFh, the command is ignored. 2. 3. The memory is now set to enter the Verify Phase. 6.3.3 Verify Phase The Verify Phase is similar to the Program Phase in that all Words must be resent to the memory for them to be checked against the programmed data. The Program/Erase Controller checks the stream of data with the data that was programmed in the Program Phase and reprograms the memory location if necessary. Three successive steps are required to execute the Verify Phase of the command. 1. Use one Bus Write operation to latch the Start Address and the first Word, to be verified. The Status Register bit SR0 should be read to check that the Program/Erase Controller is ready for the next Word. Each subsequent Word to be verified is latched with a new Bus Write operation. The Words must be written in the same order as in the Program Phase. The address can remain the Start Address or be incremented. If any address that is not in the same block as the Start Address is given with data FFFFh, the Verify Phase terminates. Status Register bit SR0 should be read to check that the P/E.C. is ready for the next Word. Finally, after all Words have been verified, write one Bus Write operation with data FFFFh to any address outside the block containing the Start Address, to terminate the Verify Phase. 2. 3. If the Verify Phase is successfully completed the memory remains in Read Status Register mode. If the Program/Erase Controller fails to reprogram a given location, the error will be signaled in the Status Register. 6.3.4 Exit Phase Status Register P/E.C. bit SR7 set to `1' indicates that the device has returned to Read mode. A full Status Register check should be done to ensure that the block has been successfully programmed. See the section on the Status Register for more details. 31/114 Command interface - Factory program commands M58WR064HU M58WR064HL 6.4 Quadruple Enhanced Factory Program command The Quadruple Enhanced Factory Program command can be used to program one or more pages of four adjacent words in parallel. The four words must differ only for the addresses ADQ0 and ADQ1. VPP must be set to VPPH during the Quadruple Enhanced Factory Program, otherwise the command will be ignored and the Status register will not output any errors. If the block being programmed is protected then the Program operation will abort, the data in the block will not be changed and the Status Register will output the error It has four phases: the Setup Phase, the Load Phase where the data is loaded into the buffer, the combined Program and Verify Phase where the loaded data is programmed to the memory and then automatically checked and reprogrammed if necessary and the Exit Phase. Unlike the Enhanced Factory Program it is not necessary to resubmit the data for the Verify Phase. The Load Phase and the Program and Verify Phase can be repeated to program any number of pages within the block. 6.4.1 Setup Phase The Quadruple Enhanced Factory Program command requires one Bus Write operation to initiate the load phase. After the setup command is issued, read operations output the Status Register data. The Read Status Register command must not be issued as it will be interpreted as data to program. 6.4.2 Load Phase The Load Phase requires 4 cycles to load the data (refer to Table 7: Factory Program commands, and Figure 30: Quadruple Enhanced Factory Program flowchart). Once the first Word of each Page is written it is impossible to exit the Load phase until all four Words have been written. Two successive steps are required to issue and execute the Load Phase of the Quadruple Enhanced Factory Program command. 1. Use one Bus Write operation to latch the Start Address and the first Word of the first Page to be programmed. For subsequent Pages the first Word address can remain the Start Address (in which case the next Page is programmed) or can be any address in the same block. If any address with data FFFFh is given that is not in the same block as the Start Address, the device enters the Exit Phase. For the first Load Phase Status Register bit SR7 should be read after the first Word has been issued to check that the command has been accepted (bit SR7 set to `0'). This check is not required for subsequent Load Phases. Each subsequent Word to be programmed is latched with a new Bus Write operation. The address is only checked for the first Word of each Page as the order of the Words to be programmed is fixed. 2. The memory is now set to enter the Program and Verify Phase. 32/114 M58WR064HU M58WR064HL Command interface - Factory program commands 6.4.3 Program and Verify Phase In the Program and Verify Phase the four Words that were loaded in the Load Phase are programmed in the memory array and then verified by the Program/Erase Controller. If any errors are found the Program/Erase Controller reprograms the location. During this phase the Status Register shows that the Program/Erase Controller is busy, Status Register bit SR7 set to `0', and that the device is not waiting for new data, Status Register bit SR0 set to `1'. When Status Register bit SR0 is set to `0' the Program and Verify phase has terminated. Once the Verify Phase has successfully completed subsequent pages in the same block can be loaded and programmed. The device returns to the beginning of the Load Phase by issuing one Bus Write operation to latch the Address and the first of the four new Words to be programmed. 6.4.4 Exit Phase Finally, after all the pages have been programmed, write one Bus Write operation with data FFFFh to any address outside the block containing the Start Address, to terminate the Load and Program and Verify Phases. Status Register bit SR7 set to `1' and bit SR0 set to `0' indicate that the Quadruple Enhanced Factory Program command has terminated. A full Status Register check should be done to ensure that the block has been successfully programmed. See the section on the Status Register for more details. If the Program and Verify Phase has successfully completed the memory returns to Read mode. If the P/E.C. fails to program and reprogram a given location, the error will be signaled in the Status Register. 33/114 Command interface - Factory program commands Table 7. Factory Program commands M58WR064HU M58WR064HL Bus Write Operations(1) Command Phase Cycles 1st Add Bank Erase Double Word Program(2) Quadruple Word Program(4) Setup, Enhanced Program Factory Program (5) Verify, Exit Setup, first Load First Program & Quadruple Verify Enhanced Subsequent Factory Loads Program (4),(5) Subsequent Program & Verify Exit 2 3 5 2+n +1 n+1 5 BKA BKA or WA1(3) BKA or WA1(3) BKA or WA1(3) WA1(8) BKA or WA1(3) Data 80h 35h 56h 30h PD1 75h 2nd Add Write WA1 WA1 Data BKA PD1 PD1 3rd Add D0h WA2 WA2 Data PD2 PD2 PD2 WA3 WAn(7) WAn(7) PD3 PAn PAn WA4 PD4 Final -1 Add Data Final Add Data BA or D0h WA1(8) PD1 WA1(6) WA2(7) PD2 WA3(7) PD3 WA1(8) PD1 WA2(9) PD2 NOT FFFF h WA1(8) NOT FFFF h WA1(8) PD4 WA3(9) PD3 WA4(9) Automatic WA2i (9) 4 WA1i(8) PD1i PD2i WA3i(9) PD3i WA4i(9) PD4i Automatic NOT FFFFh WA1(8) 1 1. WA = Word Address in targeted bank, BKA = Bank Address, PD = Program Data, BA = Block Address. 2. Word Addresses 1 and 2 must be consecutive Addresses differing only for A0. 3. Any address within the bank can be used. 4. Word Addresses 1,2,3 and 4 must be consecutive Addresses differing only for A0 and A1. 5. A Bus Read must be done between each Write cycle where the data is programmed or verified to read the Status Register and check that the memory is ready to accept the next data. n = number of Words, i = number of Pages to be programmed. 6. Any address within the block can be used. 7. Address can remain Starting Address WA1 or be incremented. 8. WA1 is the Start Address. NOT WA1 is any address that is not in the same block as WA1. 9. Address is only checked for the first Word of each Page as the order to program the Words in each page is fixed so subsequent Words in each Page can be written to any address. 34/114 M58WR064HU M58WR064HL Status Register 7 Status Register The Status Register provides information on the current or previous Program or Erase operations. Issue a Read Status Register command to read the contents of the Status Register, refer to Section 5.2: Read Status Register command for more details. To output the contents, the Status Register is latched and updated on the falling edge of the Chip Enable or Output Enable signals and can be read until Chip Enable or Output Enable returns to VIH. The Status Register can only be read using single asynchronous or single synchronous reads. Bus Read operations from any address within the bank, always read the Status Register during Program and Erase operations. The various bits convey information about the status and any errors of the operation. Bits SR7, SR6, SR2 and SR0 give information on the status of the device and are set and reset by the device. Bits SR5, SR4, SR3 and SR1 give information on errors, they are set by the device but must be reset by issuing a Clear Status Register command or a hardware reset. If an error bit is set to `1' the Status Register should be reset before issuing another command. SR7 to SR1 refer to the status of the device while SR0 refers to the status of the addressed bank. The bits in the Status Register are summarized in Table 8: Status Register bits. Refer to Table 8 in conjunction with the following text descriptions. 7.0.1 Program/Erase Controller Status Bit (SR7) The Program/Erase Controller Status bit indicates whether the Program/Erase Controller is active or inactive in any bank. When the Program/Erase Controller Status bit is Low (set to `0'), the Program/Erase Controller is active; when the bit is High (set to `1'), the Program/Erase Controller is inactive, and the device is ready to process a new command. The Program/Erase Controller Status is Low immediately after a Program/Erase Suspend command is issued until the Program/Erase Controller pauses. After the Program/Erase Controller pauses the bit is High. During Program, Erase, operations the Program/Erase Controller Status bit can be polled to find the end of the operation. Other bits in the Status Register should not be tested until the Program/Erase Controller completes the operation and the bit is High. After the Program/Erase Controller completes its operation the Erase Status, Program Status, VPP Status and Block Lock Status bits should be tested for errors. 7.0.2 Erase Suspend Status Bit (SR6) The Erase Suspend Status bit indicates that an Erase operation has been suspended or is going to be suspended in the addressed block. When the Erase Suspend Status bit is High (set to `1'), a Program/Erase Suspend command has been issued and the memory is waiting for a Program/Erase Resume command. The Erase Suspend Status should only be considered valid when the Program/Erase Controller Status bit is High (Program/Erase Controller inactive). SR7 is set within the Erase Suspend Latency time of the Program/Erase Suspend command being issued therefore the memory may still complete the operation rather than entering the Suspend mode. When a Program/Erase Resume command is issued the Erase Suspend Status bit returns Low. 35/114 Status Register M58WR064HU M58WR064HL 7.0.3 Erase Status Bit (SR5) The Erase Status bit can be used to identify if the memory has failed to verify that the block or bank has erased correctly. When the Erase Status bit is High (set to `1'), the Program/Erase Controller has applied the maximum number of pulses to the block or bank and still failed to verify that it has erased correctly. The Erase Status bit should be read once the Program/Erase Controller Status bit is High (Program/Erase Controller inactive). Once set High, the Erase Status bit can only be reset Low by a Clear Status Register command or a hardware reset. If set High it should be reset before a new Program or Erase command is issued, otherwise the new command will appear to fail. 7.0.4 Program Status Bit (SR4) The Program Status bit is used to identify either a Program failure, or an attempt to program a `1' to an already programmed bit when VPP = VPPH. When the Program Status bit goes High (set to `1') after a Program failure, the Program/Erase Controller has applied the maximum number of pulses to the byte and still failed to verify that it has programmed correctly. After an attempt to program a `1' to an already programmed bit, the Program Status bit SR4 only goes High (set to '1') if VPP = VPPH (if VPP VPPH, SR4 remains Low (set to `0') and the attempt is not shown). The Program Status bit should be read once the Program/Erase Controller Status bit is High (Program/Erase Controller inactive). Once set High, the Program Status bit can only be reset Low by a Clear Status Register command or a hardware reset. If set High it should be reset before a new command is issued, otherwise the new command will appear to fail. 7.0.5 VPP Status Bit (SR3) The VPP Status bit can be used to identify an invalid voltage on the VPP pin during Program and Erase operations. The VPP pin is only sampled at the beginning of a Program or Erase operation. Indeterminate results can occur if VPP becomes invalid during an operation. When the VPP Status bit is Low (set to `0'), the voltage on the VPP pin was sampled at a valid voltage; when the VPP Status bit is High (set to `1'), the VPP pin has a voltage that is below the VPP Lockout Voltage, VPPLK, the memory is protected and Program and Erase operations cannot be performed. Once set High, the VPP Status bit can only be reset Low by a Clear Status Register command or a hardware reset. If set High it should be reset before a new Program or Erase command is issued, otherwise the new command will appear to fail. 36/114 M58WR064HU M58WR064HL Status Register 7.0.6 Program Suspend Status Bit (SR2) The Program Suspend Status bit indicates that a Program operation has been suspended in the addressed block. When the Program Suspend Status bit is High (set to `1'), a Program/Erase Suspend command has been issued and the memory is waiting for a Program/Erase Resume command. The Program Suspend Status should only be considered valid when the Program/Erase Controller Status bit is High (Program/Erase Controller inactive). SR2 is set within the Program Suspend Latency time of the Program/Erase Suspend command being issued therefore the memory may still complete the operation rather than entering the Suspend mode. When a Program/Erase Resume command is issued the Program Suspend Status bit returns Low. 7.0.7 Block Protection Status Bit (SR1) The Block Protection Status bit can be used to identify if a Program or Block Erase operation has tried to modify the contents of a locked block. When the Block Protection Status bit is High (set to `1'), a Program or Erase operation has been attempted on a locked block. Once set High, the Block Protection Status bit can only be reset Low by a Clear Status Register command or a hardware reset. If set High it should be reset before a new command is issued, otherwise the new command will appear to fail. 7.0.8 Bank Write/Multiple Word Program Status Bit (SR0) The Bank Write Status bit indicates whether the addressed bank is programming or erasing. In Enhanced Factory Program mode the Multiple Word Program bit shows if a Word has finished programming or verifying depending on the phase. The Bank Write Status bit should only be considered valid when the Program/Erase Controller Status SR7 is Low (set to `0'). When both the Program/Erase Controller Status bit and the Bank Write Status bit are Low (set to `0'), the addressed bank is executing a Program or Erase operation. When the Program/Erase Controller Status bit is Low (set to `0') and the Bank Write Status bit is High (set to `1'), a Program or Erase operation is being executed in a bank other than the one being addressed. In Enhanced Factory Program mode if Multiple Word Program Status bit is Low (set to `0'), the device is ready for the next Word, if the Multiple Word Program Status bit is High (set to `1') the device is not ready for the next Word. Note: Refer to Appendix C: Flowcharts and pseudo codes, for using the Status Register. 37/114 Status Register Table 8. Bit M58WR064HU M58WR064HL Status Register bits Name Type Logic Level (1) '1' Ready Busy Erase Suspended Erase In progress or Completed Erase Error Erase Success Program Error Program Success VPP Invalid, Abort VPP OK Program Suspended Program In Progress or Completed Program/Erase on protected Block, Abort No operation to protected blocks SR7 = `1' Not Allowed '1' SR7 = `0' Bank Write Status Status SR7 = `1' '0' SR7 = `0' Program or erase operation in a bank other than the addressed bank No Program or erase operation in the device Program or erase operation in addressed bank Definition SR7 P/E.C. Status Status '0' '1' SR6 Erase Suspend Status Status '0' '1' SR5 Erase Status Error '0' '1' SR4 Program Status Error '0' '1' SR3 VPP Status Program Suspend Status Block Protection Status Error '0' '1' Status '0' '1' Error '0' SR2 SR1 SR0 SR7 = `1' Not Allowed Multiple Word Program Status (Enhanced Factory Program mode) '1' SR7 = `0' Status '0' SR7 = `0' 1. Logic level '1' is High, '0' is Low. the device is NOT ready for the next word SR7 = `1' the device is exiting from EFP the device is ready for the next Word 38/114 M58WR064HU M58WR064HL Configuration Register 8 Configuration Register The Configuration Register is used to configure the type of bus access that the memory will perform. Refer to Section 9: Read modes for details on read operations. The Configuration Register is set through the Command Interface. After a Reset or PowerUp the device is configured for asynchronous read (CR15 = 1). The Configuration Register bits are described in Table 10. They specify the selection of the burst length, burst type, burst X latency and the Read operation. Refer to Figures 5 and 6 for examples of synchronous burst configurations. 8.1 Read Select Bit (CR15) The Read Select bit, CR15, is used to switch between asynchronous and synchronous Bus Read operations. When the Read Select bit is set to '1', read operations are asynchronous; when the Read Select bit is set to '0', read operations are synchronous. Synchronous Burst Read is supported in both parameter and main blocks and can be performed across banks. On reset or power-up the Read Select bit is set to'1' for asynchronous access. 8.2 Bus Invert Configuration (CR14) The Bus Invert Configuration bit is used to enable the BINV functionality. When the functionality is enabled, if the BINV pin operates as an input pin (during write bus operations), the BINV signal must always be driven; if it operates as an output pin (during read bus operations), the functionality is valid only during synchronous read operations. 8.3 X-Latency Bits (CR13-CR11) The X-Latency bits are used during Synchronous Read operations to set the number of clock cycles between the address being latched and the first data becoming available. Refer to Figure 5: X-latency and data output configuration example. For correct operation the X-Latency bits can only assume the values in Table 10: Configuration Register. Table 9 shows how to set the X-Latency parameter, taking into account the speed class of the device and the Frequency used to read the Flash memory in Synchronous mode. Table 9. X-Latency Settings X-Latency min fmax 30MHz 40MHz 54MHz 66MHz tKmin Speed 70ns 33ns 25ns 19ns 15ns 2 3 4 4 39/114 Configuration Register M58WR064HU M58WR064HL 8.4 Wait Polarity Bit (CR10) In synchronous burst mode the Wait signal indicates whether the output data are valid or a WAIT state must be inserted. The Wait Polarity bit is used to set the polarity of the Wait signal. When the Wait Polarity bit is set to `0' the Wait signal is active Low. When the Wait Polarity bit is set to `1', the Wait signal is active High. 8.5 Data Output Configuration Bit (CR9) The Data Output Configuration bit determines whether the output remains valid for one or two clock cycles. When the Data Output Configuration Bit is '0' the output data is valid for one clock cycle, when the Data Output Configuration Bit is '1' the output data is valid for two clock cycles. The Data Output Configuration depends on the condition: tK > tKQV + tQVK_CPU where tK is the clock period, tQVK_CPU is the data setup time required by the system CPU and tKQV is the clock to data valid time. If this condition is not satisfied, the Data Output Configuration bit should be set to `1' (two clock cycles). Refer to Figure 5: X-latency and data output configuration example. 8.6 Wait Configuration Bit (CR8) In burst mode the Wait bit controls the timing of the Wait output pin, WAIT. When WAIT is asserted, Data is Not Valid and when WAIT is deasserted, Data is Valid. When the Wait bit is '0' the Wait output pin is asserted during the wait state. When the Wait bit is '1', the Wait output pin is asserted one clock cycle before the wait state. 8.7 Burst Type Bit (CR7) The Burst Type bit is used to configure the sequence of addresses read as sequential or interleaved. When the Burst Type bit is '0' the memory outputs from interleaved addresses; when the Burst Type bit is '1', the memory outputs from sequential addresses. See Table 11: Burst type definition, for the sequence of addresses output from a given starting address in each mode. 8.8 Valid Clock Edge Bit (CR6) The Valid Clock Edge bit, CR6, is used to configure the active edge of the Clock, K, during Synchronous Burst Read operations. When the Valid Clock Edge bit is '0' the falling edge of the Clock is the active edge; when the Valid Clock Edge bit is '1' the rising edge of the Clock is active. 40/114 M58WR064HU M58WR064HL Configuration Register 8.9 Power-Down Bit (CR5) The Power-Down bit is used to enable or disable the Power-Down function. When it is set to `0' the Power-Down function is disabled. If the Reset/Power-Down, RP, pin goes Low (VIL), the device is reset and the supply current IDD is reduced to the Standby value IDD3. When the Power-Down bit is set to `1' the Power-Down function is enabled. If the Reset/PowerDown, RP, pin goes Low (VIL) the device switches to the Power-Down state and the supply current IDD is reduced to the Reset/Power-Down value, IDD2. The recovery time after a Reset/Power-Down, RP, pulse is significantly longer when PowerDown is enabled (see Table 26). 8.10 Wrap Burst Bit (CR3) The burst reads can be confined inside the 4, 8 or 16 Word boundary (wrap) or overcome the boundary (no wrap). The Wrap Burst bit is used to select between wrap and no wrap. When the Wrap Burst bit is set to `0' the burst read wraps; when it is set to `1' the burst read does not wrap. 8.11 Burst length Bits (CR2-CR0) The Burst Length bits set the number of Words to be output during a Synchronous Burst Read operation as result of a single address latch cycle. They can be set for 4 words, 8 words, 16 words or continuous burst, where all the words are read sequentially. In continuous burst mode the burst sequence can cross bank boundaries. In continuous burst mode or in 4, 8, 16 words no-wrap, depending on the starting address, the device asserts the WAIT output to indicate that a delay is necessary before the data is output. If the starting address is aligned to a 4 word boundary no wait states are needed and the WAIT output is not asserted. If the starting address is shifted by 1,2 or 3 positions from the four word boundary, WAIT will be asserted for 1, 2 or 3 clock cycles when the burst sequence crosses the first 16 word boundary, to indicate that the device needs an internal delay to read the successive words in the array. WAIT will be asserted only once during a continuous burst access. See also Table 11: Burst type definition. CR4 is reserved for future use. 41/114 Configuration Register Table 10. Bit CR15 M58WR064HU M58WR064HL Configuration Register Description 0 Read Select 1 Asynchronous Read (Default at power-on) BINV (power save) disabled (default) BINV (power save) enabled 2 clock latency 3 clock latency 4 clock latency 5 clock latency Reserved (default) Bus invert configuration 0 1 010 011 100 Value Synchronous Read Description CR14 CR13-CR11 X-Latency 101 111 Other configurations reserved 0 CR10 Wait Polarity 1 CR9 Data Output Configuration Wait Configuration 1 0 CR7 Burst Type 1 0 CR6 Valid Clock Edge 1 CR5 CR4 CR3 Power-Down Configuration Reserved 0 Wrap Burst 1 001 010 CR2-CR0 Burst Length 011 111 16 words Continuous (CR7 must be set to `1') (default) No Wrap (default) 4 words 8 words Wrap 0 1 Rising Clock edge (default) Power-Down disabled (default) Power-Down enabled Sequential (default) Falling Clock edge WAIT is active one data cycle before wait state Interleaved 0 1 0 CR8 WAIT is active high Data held for one clock cycle Data held for two clock cycles (default) WAIT is active during wait state (default) WAIT is active Low (default) 42/114 M58WR064HU M58WR064HL Table 11. Mode Start Add Configuration Register Burst type definition 4 Words 8 Words 16 Words Sequential Interleaved Continuous Burst Sequential Interleaved Sequential Interleaved 0-1-2-3-45-6-7 0-1-2-3-4-56-7 0 0-1-2-3 0-1-2-3 0-1-2-3-4-50-1-2-3-4-5-6-76-7-8-9-108-9-10-11-1211-12-13-1413-14-15 15 0-1-2-3-4-5-6... 1 1-2-3-0 1-0-3-2 1-2-3-4-56-7-0 1-0-3-2-5-41-2-3-4-5-6-7-81-0-3-2-5-47-6-9-8-119-10-11-12-137-6 10-13-12-1514-15-0 14 2-3-0-1-6-72-3-4-5-6-7-8-92-3-0-1-6-74-5-10-11-810-11-12-13-144-5 9-14-15-1215-0-1 13 1-2-3-4-5-6-7...15-WAIT-1617-18... 2-3-4-5-6-7...15WAIT-WAIT-1617-18... 2 2-3-0-1 2-3-0-1 2-3-4-5-67-0-1 3 Wrap 3-0-1-2 3-2-1-0 3-4-5-6-70-1-2 3-2-1-0-7-63-4-5-6-7-8-93-4-5-6-7...153-2-1-0-7-65-4-11-10-910-11-12-13-14WAIT-WAIT5-4 8-15-14-1315-0-1-2 WAIT-16-17-18... 12 ... 7-0-1-2-34-5-6 7-6-5-4-3-27-8-9-10-11-127-6-5-4-3-21-0-15-1413-14-15-0-1-21-0 13-12-11-103-4-5-6 9-8 7-8-9-10-11-1213-14-15-WAITWAIT-WAIT-1617... 7 7-4-5-6 7-6-5-4 ... 12 13 12-13-14-15-1617-18... 13-14-15-WAIT16-17-18... 14-15-WAITWAIT-16-1718.... 15-WAIT-WAITWAIT-16-17-18... 14 15 43/114 Configuration Register Table 11. Mode Start Add M58WR064HU M58WR064HL Burst type definition (continued) 4 Words 8 Words 16 Words Sequential 0-1-2-3-4-5-6-78-9-10-11-1213-14-15 1-2-3-4-5-6-7-89-10-11-12-1314-15-WAIT-16 2-3-4-5-6-7-8-910-11-12-13-1415-WAIT-WAIT16-17 3-4-5-6-7-8-910-11-12-13-1415-WAIT-WAITWAIT16-17-18 Interleaved Continuous Burst Sequential Interleaved Sequential Interleaved 0-1-2-3 0-1-2-3-45-6-7 1-2-3-4-56-7-8 0 1 1-2-3-4 2 2-3-4-5 2-3-4-5-67-8-9... 3 3-4-5-6 3-4-5-6-78-9-10 ... 7-8-9-1011-12-1314 7-8-9-10-11-1213-14-15-WAITWAIT-WAIT-1617-18-19-20-2122 Same as for Wrap (Wrap /No Wrap has no effect on Continuous Burst) No-wrap 7 7-8-9-10 ... 12-13-1415 12-13-1415-16-1718-19 13-14-15WAIT-1617-18-1920 14-15WAITWAIT-1617-18-1920-21 15-WAITWAITWAIT-1617-18-1920-21-22 12-13-14-15-1617-18-19-20-2122-23-24-25-2627 13-14-15-WAIT16-17-18-19-2021-22-23-24-2526-27-28 14-15-WAITWAIT-16-17-1819-20-21-22-2324-25-26-27-2829 15-WAIT-WAITWAIT-16-17-1819-20-21-22-2324-25-26-27-2829-30 12 13 13-14-15WAIT-16 14 14-15WAITWAIT-1617 15-WAITWAITWAIT-1617-18 15 44/114 M58WR064HU M58WR064HL Figure 5. X-latency and data output configuration example X-latency 1st cycle K 2nd cycle 3rd cycle 4th cycle Configuration Register E L A21-A16 VALID ADDRESS tQVK_CPU tKQV tK ADQ15-ADQ0 VALID ADDRESS VALID DATA VALID DATA AI10977b 1. Settings shown: X-latency = 4, Data Output held for one clock cycle. 45/114 Configuration Register Figure 6. E M58WR064HU M58WR064HL Wait configuration example K L G A21-A16 VALID ADDRESS ADQ15-ADQ0 VALID ADDRESS VALID DATA VALID DATA NOT VALID VALID DATA WAIT CR8 = '0' CR10 = '0' WAIT CR8 = '1' CR10 = '0' WAIT CR8 = '0' CR10 = '1' WAIT CR8 = '1' CR10 = '1' AI10560b 46/114 M58WR064HU M58WR064HL Read modes 9 Read modes Read operations can be performed in two different ways depending on the settings in the Configuration Register. If the clock signal is `don't care' for the data output, the read operation is Asynchronous; if the data output is synchronized with clock, the read operation is Synchronous. The Read mode and data output format are determined by the Configuration Register. (See Section 8: Configuration Register for details). All banks supports both asynchronous and synchronous read operations. The Multiple Bank architecture allows read operations in one bank, while write operations are being executed in another (see Tables 12 and 13). 9.1 Asynchronous Read mode In Asynchronous Read operations the clock signal is `don't care'. The device outputs the data corresponding to the address latched, that is the memory array, Status Register, Common Flash Interface or Electronic Signature depending on the command issued. CR15 in the Configuration Register must be set to `1' for Asynchronous operations. In Asynchronous Read mode, the WAIT signal is always deasserted. The device features an Automatic Standby mode. During asynchronous read operations, after a bus inactivity of 150ns, the device automatically switches to the Automatic Standby mode. In this condition the power consumption is reduced to the standby value IDD4 and the outputs are still driven. See Table 22: Asynchronous read AC characteristics, and Figure 9: Asynchronous random access read AC waveforms. 47/114 Read modes M58WR064HU M58WR064HL 9.2 Synchronous Burst Read mode In Synchronous Burst Read mode the data is output in bursts synchronized with the clock. It is possible to perform burst reads across bank boundaries. Synchronous Burst Read mode can only be used to read the memory array. For other read operations, such as Read Status Register, Read CFI and Read Electronic Signature, Single Synchronous Read or Asynchronous Random Access Read must be used. In Synchronous Burst Read mode the flow of the data output depends on parameters that are configured in the Configuration Register. A burst sequence is started at the first clock edge (rising or falling depending on Valid Clock Edge bit CR6 in the Configuration Register) after the falling edge of Latch Enable. Addresses are internally incremented and after a delay of 2 to 5 clock cycles (X latency bits CR13-CR11) the corresponding data are output on each clock cycle. The number of Words to be output during a Synchronous Burst Read operation can be configured as 4, 8 or 16 Words or Continuous (Burst Length bits CR2-CR0). The data can be configured to remain valid for one or two clock cycles (Data Output Configuration bit CR9). The order of the data output can be modified through the Burst Type and the Wrap Burst bits in the Configuration Register. The burst sequence may be configured to be sequential or interleaved (CR7). The burst reads can be confined inside the 4, 8 or 16 Word boundary (Wrap) or overcome the boundary (No Wrap). If the starting address is aligned to the Burst Length (4, 8 or 16 Words), the wrapped configuration has no impact on the output sequence. Interleaved mode is not allowed in Continuous Burst Read mode or with No Wrap sequences. A WAIT signal may be asserted to indicate to the system that an output delay will occur. This delay will depend on the starting address of the burst sequence; the worst case delay will occur when the sequence is crossing a 16 word boundary and the starting address was at the end of a four word boundary. WAIT is asserted during X-latency, the Wait state and at the end of a 4, 8 and 16 Word burst. It is only deasserted when output data are valid or when G is at VIH. In Continuous Burst Read mode a Wait state will occur when crossing the first 16 Word boundary. If the burst starting address is aligned to a 4 Word Page, the Wait state will not occur. The WAIT signal can be configured to be active Low or active High by setting CR10 in the Configuration Register. See Table 23: Synchronous read AC characteristics, and Figure 10: Synchronous burst read AC waveforms, for details. 48/114 M58WR064HU M58WR064HL Read modes 9.2.1 Synchronous Burst Read Suspend A Synchronous Burst Read operation can be suspended, freeing the data bus for other higher priority devices. It can be suspended during the initial access latency time (before data is output), or after the device has output data. When the Synchronous Burst Read operation is suspended, internal array sensing continues and any previously latched internal data is retained. A burst sequence can be suspended and resumed as often as required as long as the operating conditions of the device are met. A Synchronous Burst Read operation is suspended when E is low and the current address has been latched (on a Latch Enable rising edge or on a valid clock edge). The clock signal is then halted at VIH or at VIL, and G goes high. When G becomes low again and the clock signal restarts, the Synchronous Burst Read operation is resumed exactly where it stopped. WAIT being gated by E remains active and will not revert to high-impedance when G goes high. So if two or more devices are connected to the system's READY signal, to prevent bus contention the WAIT signal of the Flash memory should not be directly connected to the system's READY signal. See Table 23: Synchronous read AC characteristics, and Figure 12: Synchronous burst read suspend AC waveforms, for details. 9.3 Single Synchronous Read mode Single Synchronous Read operations are similar to Synchronous Burst Read operations except that only the first data output after the X latency is valid. Synchronous Single Reads are used to read the Electronic Signature, Status Register, CFI, Block Protection Status, Configuration Register Status or Protection Register. When the addressed bank is in Read CFI, Read Status Register or Read Electronic Signature mode, the WAIT signal is deasserted when Output Enable, G, is at VIH or for the one clock cycle during which output data is valid. Otherwise, it is asserted. See Table 23: Synchronous read AC characteristics, and Figure 11: Single synchronous read AC waveforms, for details. 49/114 Dual operations and multiple bank architecture M58WR064HU M58WR064HL 10 Dual operations and multiple bank architecture The Multiple Bank Architecture of the M58WR064HU/L provides flexibility for software developers by allowing code and data to be split with 4Mbit granularity. The Dual Operations feature simplifies the software management of the device and allows code to be executed from one bank while another bank is being programmed or erased. The Dual operations feature means that while programming or erasing in one bank, Read operations are possible in another bank with zero latency (only one bank at a time is allowed to be in Program or Erase mode). If a Read operation is required in a bank which is programming or erasing, the Program or Erase operation can be suspended. Also if the suspended operation was Erase then a Program command can be issued to another block, so the device can have one block in Erase Suspend mode, one programming and other banks in Read mode. Bus Read operations are allowed in another bank between setup and confirm cycles of program or erase operations. The combination of these features means that read operations are possible at any moment. Dual operations between the Parameter Bank and the CFI, OTP or Electronic Signature memory space, are not allowed. Table 14: Dual operation limitations shows which dual operations are allowed between the CFI, OTP, Electronic Signature locations and the memory array. Tables 12 and 13 show the dual operations possible in other banks and in the same bank. Note that only the commonly used commands are represented in these tables. For a complete list of possible commands refer to Appendix D: Command interface state tables. Table 12. Status of bank Dual operations allowed in other banks Commands allowed in another bank Read Array Yes Yes Yes Yes Yes Read Read Read Status CFI Electronic Register Query Signature Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Block Erase Yes - - - - Program/ Program/ Erase Erase Suspend Resume Yes Yes Yes - - Yes - - Yes Yes Program Yes - - - Yes Idle Programming Erasing Program Suspended Erase Suspended 50/114 M58WR064HU M58WR064HL Table 13. Status of bank Dual operations and multiple bank architecture Dual operations allowed in same bank Commands allowed in same bank Read Array Yes - (1) (1) Read Status Register Yes Yes Yes Yes Yes Read CFI Query Yes Yes Yes Yes Yes Read Electronic Program Signature Yes Yes Yes Yes Yes Yes - - - Yes(2) Block Erase Yes - - - - Program/ Program/ Erase Erase Suspend Resume Yes Yes Yes - - Yes - - Yes Yes Idle Programming Erasing Program Suspended Erase Suspended - Yes(2) Yes(2) 1. The Read Array command is accepted but the data output is not guaranteed until the Program or Erase has completed. 2. Not allowed in the Block or Word that is being erased or programmed. Table 14. Dual operation limitations Commands allowed Read Main Blocks Current Status Read CFI / OTP / Electronic Signature Read Parameter Blocks Located in Parameter Bank No Not Located in Parameter Bank Yes Programming / Erasing Parameter Blocks Located in Parameter Bank Not Located in Parameter Bank No No Yes No No Yes Programming / Erasing Main Blocks Yes No Yes No Yes No In Different Bank Only No Programming OTP 51/114 Block locking M58WR064HU M58WR064HL 11 Block locking The M58WR064HU/L features an instant, individual block locking scheme that allows any block to be locked or unlocked with no latency. This locking scheme has three levels of protection. Lock/Unlock - this first level allows software-only control of block locking. Lock-Down - this second level requires hardware interaction before locking can be changed. VPP VPPLK - the third level offers a complete hardware protection against program and erase on all blocks. The protection status of each block can be set to Locked, Unlocked, and Lock-Down. Table 15, defines all of the possible protection states (WP, DQ1, DQ0), and Appendix C, Figure 27, shows a flowchart for the locking operations. 11.1 Reading a block's lock status The lock status of every block can be read in the Read Electronic Signature mode of the device. To enter this mode write 90h to the device. Subsequent reads at the address specified in Table 6, will output the protection status of that block. The lock status is represented by DQ0 and DQ1. DQ0 indicates the Block Lock/Unlock status and is set by the Lock command and cleared by the Unlock command. It is also automatically set when entering Lock-Down. DQ1 indicates the Lock-Down status and is set by the Lock-Down command. It cannot be cleared by software, only by a hardware reset or power-down. The following sections explain the operation of the locking system. 11.2 Locked state The default status of all blocks on power-up or after a hardware reset is Locked (states (0,0,1) or (1,0,1)). Locked blocks are fully protected from any program or erase. Any program or erase operations attempted on a locked block will return an error in the Status Register. The Status of a Locked block can be changed to Unlocked or Lock-Down using the appropriate software commands. An Unlocked block can be Locked by issuing the Lock command. 11.3 Unlocked state Unlocked blocks (states (0,0,0), (1,0,0) (1,1,0)), can be programmed or erased. All unlocked blocks return to the Locked state after a hardware reset or when the device is powereddown. The status of an unlocked block can be changed to Locked or Locked-Down using the appropriate software commands. A locked block can be unlocked by issuing the Unlock command. 52/114 M58WR064HU M58WR064HL Block locking 11.4 Lock-Down state Blocks that are Locked-Down (state (0,1,x))are protected from program and erase operations (as for Locked blocks) but their protection status cannot be changed using software commands alone. A Locked or Unlocked block can be Locked-Down by issuing the Lock-Down command. Locked-Down blocks revert to the Locked state when the device is reset or powered-down. The Lock-Down function is dependent on the WP input pin. When WP=0 (VIL), the blocks in the Lock-Down state (0,1,x) are protected from program, erase and protection status changes. When WP=1 (VIH) the Lock-Down function is disabled (1,1,x) and Locked-Down blocks can be individually unlocked to the (1,1,0) state by issuing the software command, where they can be erased and programmed. These blocks can then be re-locked (1,1,1) and unlocked (1,1,0) as desired while WP remains high. When WP is Low, blocks that were previously Locked-Down return to the Lock-Down state (0,1,x) regardless of any changes made while WP was High. Device reset or power-down resets all blocks, including those in Lock-Down, to the Locked state. 11.5 Locking operations during Erase Suspend Changes to block lock status can be performed during an erase suspend by using the standard locking command sequences to unlock, lock or lock-down a block. This is useful in the case when another block needs to be updated while an erase operation is in progress. To change block locking during an erase operation, first write the Erase Suspend command, then check the status register until it indicates that the erase operation has been suspended. Next write the desired Lock command sequence to a block and the lock status will be changed. After completing any desired lock, read, or program operations, resume the erase operation with the Erase Resume command. If a block is locked or locked-down during an erase suspend of the same block, the locking status bits will be changed immediately, but when the erase is resumed, the erase operation will complete. Locking operations cannot be performed during a program suspend. Refer to Appendix D: Command interface state tables, for detailed information on which commands are valid during erase suspend. 53/114 Block locking Table 15. Lock status M58WR064HU M58WR064HL Current Protection Status(1) (WP, ADQ1, ADQ0) Program/Erase Allowed yes no yes no yes no no After Block Lock Command 1,0,1 1,0,1 1,1,1 1,1,1 0,0,1 0,0,1 0,1,1 Next Protection Status(1) (WP, ADQ1, ADQ0) After Block Unlock Command 1,0,0 1,0,0 1,1,0 1,1,0 0,0,0 0,0,0 0,1,1 After Block Lock-Down Command 1,1,1 1,1,1 1,1,1 1,1,1 0,1,1 0,1,1 0,1,1 After WP transition 0,0,0 0,0,1 0,1,1 0,1,1 1,0,0 1,0,1 1,1,1 or 1,1,0(3) Current State 1,0,0 1,0,1(2) 1,1,0 1,1,1 0,0,0 0,0,1(2) 0,1,1 1. The lock status is defined by the write protect pin and by DQ1 (`1' for a locked-down block) and DQ0 (`1' for a locked block) as read in the Read Electronic Signature command with A1 = VIH and A0 = VIL. 2. All blocks are locked at power-up, so the default configuration is 001 or 101 according to WP status. 3. A WP transition to VIH on a locked block will restore the previous DQ0 value, giving a 111 or 110. 54/114 M58WR064HU M58WR064HL Program and erase times and endurance cycles 12 Program and erase times and endurance cycles The Program and Erase times and the number of Program/ Erase cycles per block are shown in Table 16. In the M58WR064HU/L the maximum number of Program/ Erase cycles depends on the voltage supply used. Table 16. Program, erase times and endurance cycles(1) Parameter Condition Parameter Block (4 KWord)(2) Min Typ 0.3 0.8 1 4.5 6 12 40 300 5 5 100,000 100,000 0.25 0.8 6 Word(4) 10 11 38 8 32 88 300 64 256 (4) Typical after 100k W/E Cycles 1 3 Max 2.5 4 4 Unit s s s s s Erase Main Block Preprogrammed (32 KWord) Not Preprogrammed Bank (4Mbit) Word (3) Preprogrammed Not Preprogrammed VPP = VDD 12 100 s ms ms Program Parameter Block (4 KWord) Main Block (32 KWord) Program Erase Suspend Latency 10 20 s s cycles cycles Main Blocks Program/Erase Cycles (per Block) Parameter Blocks Parameter Block (4 KWord) Erase Main Block (32 KWord) Bank (4Mbit) Word/ Double Word/ Quadruple Parameter Block (4 KWord) Program (3) 2.5 4 100 s s s s ms ms ms ms ms ms ms ms s s Quad-Enhanced Factory Enhanced Factory Quadruple Word Word Quad-Enhanced Factory Main Block (32 KWord) Quadruple Word(4) Word Bank (4Mbit) Main Blocks Quad-Enhanced Factory Quadruple Word(4) Enhanced Factory (4) VPP = VPPH 0.7 0.5 Program/Erase Cycles (per Block) Parameter Blocks 1. TA = -40 to 85C; VDD = VDDQ = 1.7V to 2V. 2. The difference between Preprogrammed and not preprogrammed is not significant (30ms). 1000 cycles 2500 cycles 3. Values are liable to change with the external system-level overhead (command sequence and Status Register polling execution). 4. Measurements performed at 25C. TA = 30C 10C for Quadruple Word, Double Word and Quadruple Enhanced Factory Program. 55/114 Maximum rating M58WR064HU M58WR064HL 13 Maximum rating Stressing the device above the rating listed in the Absolute Maximum Ratings table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the Numonyx SURE Program and other relevant quality documents. Table 17. Symbol TA TBIAS TSTG VIO VDD VDDQ VPP IO tVPPH Absolute maximum ratings Value Parameter Min Ambient Operating Temperature Temperature Under Bias Storage Temperature Input or Output Voltage Supply Voltage Input/Output Supply Voltage Program Voltage Output Short Circuit Current Time for VPP at VPPH -40 -40 -65 -0.5 -0.2 -0.2 -0.2 Max 85 125 155 VDDQ+0.6 2.45 2.45 14 100 100 C C C V V V V mA hours Unit 56/114 M58WR064HU M58WR064HL DC and AC parameters 14 DC and AC parameters This section summarizes the operating measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics Tables that follow, are derived from tests performed under the Measurement Conditions summarized in Table 18: Operating and AC measurement conditions. Designers should check that the operating conditions in their circuit match the operating conditions when relying on the quoted parameters. Table 18. Operating and AC measurement conditions M58WR064HU/L Parameter Min VDD Supply Voltage VDDQ Supply Voltage VPP Supply Voltage (Factory environment) VPP Supply Voltage (Application environment) Ambient Operating Temperature Load Capacitance (CL) Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Ref. Voltages 0 to VDDQ VDDQ/2 1.7 1.7 8.5 -0.4 -40 30 5 70 Max 2 2 12.6 VDDQ+0.4 85 V V V V C pF ns V V Units Figure 7. AC measurement I/O waveform VDDQ VDDQ/2 0V AI06161 57/114 DC and AC parameters Figure 8. AC measurement load circuit VDDQ M58WR064HU M58WR064HL VDDQ VDD 16.7k DEVICE UNDER TEST 0.1F 0.1F CL 16.7k CL includes JIG capacitance AI06162 Table 19. Symbol CIN COUT Capacitance(1) Parameter Input Capacitance Output Capacitance Test Condition VIN = 0V VOUT = 0V Min 6 8 Max 8 12 Unit pF pF 1. Sampled only, not 100% tested. 58/114 M58WR064HU M58WR064HL Table 20. Symbol ILI ILO DC and AC parameters DC Characteristics - Currents Parameter Input Leakage Current Output Leakage Current Supply Current Asynchronous Read (f=6MHz) Test Condition 0V VIN VDDQ 0V VOUT VDDQ E = VIL, G = VIH 4 Word 10 18 20 25 28 2 22 22 8 10 8 10 20 Min Typ Max 1 1 20 20 22 27 30 10 50 50 15 20 15 20 40 Unit A A mA mA mA mA mA A A A mA mA mA mA mA IDD1 Supply Current Synchronous Read (f=66MHz) 8 Word 16 Word Continuous IDD2 IDD3 IDD4 Supply Current (Reset/Power-Down) Supply Current (Standby) Supply Current (Automatic Standby) Supply Current (Program) RP = VSS 0.2V K=VSS E = VDDQ 0.2V E = VIL, G = VIH VPP = VPPH VPP = VDD IDD5(1) Supply Current (Erase) VPP = VPPH VPP = VDD Program/Erase in one Bank, Asynchronous Read in another Bank Program/Erase in one Bank, Synchronous Read (continuous burst 66MHz) in another Bank K=VSS E = VDDQ 0.2V VPP = VPPH VPP = VDD VPP = VPPH VPP = VDD VPP = VPPH VPP VDD VPP VDD IDD6(1)(2) Supply Current (Dual Operations) 38 50 mA IDD7(1) Supply Current Program/ Erase Suspended (Standby) VPP Supply Current (Program) 22 5 0.2 5 0.2 100 0.2 0.2 50 10 5 10 5 400 5 5 A mA A mA A A A A IPP1(1) VPP Supply Current (Erase) IPP2 IPP3(1) VPP Supply Current (Read) VPP Supply Current (Standby) 1. Sampled only, not 100% tested. 2. VDD Dual Operation current is the sum of read and program or erase currents. 59/114 DC and AC parameters Table 21. Symbol VIL VIH VOL VOH VPP1 VPPH VPPLK VLKO VRPH M58WR064HU M58WR064HL DC characteristics - voltages Parameter Test Condition Min -0.5 VDDQ -0.4 IOL = 100A IOH = -100A Program, Erase Program, Erase VDDQ -0.1 1.3 8.5 12 2.4 12.6 0.9 1 3.3 Typ Max 0.4 VDDQ + 0.4 0.1 Unit V V V V V V V V V Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage VPP Program Voltage-Logic VPP Program Voltage Factory Program or Erase Lockout VDD Lock Voltage RP pin Extended High Voltage 60/114 M58WR064HU M58WR064HL Figure 9. Asynchronous random access read AC waveforms tAVQV ADQ0-ADQ15 VALID ADDRESS DC and AC parameters Hi-Z VALID DATA A16-A21 VALID ADDRESS tAVAV tAVLH tLHAX VALID L tLLLH tLLQV tELLH tELQV E tEHQZ tEHQX G tGLQV tGLQX tELTV WAIT Hi-Z tGHQX tGHQZ tEHTZ tLHGL Valid Address Latch Outputs Enabled Data Valid Standby AI12825 1. Write Enable, W, is High, WAIT is active Low. 61/114 DC and AC parameters Table 22. Symbol tAVAV tAVQV tELTV tELQV (2) M58WR064HU M58WR064HL Asynchronous read AC characteristics M58WR064HU/L Alt tRC tACC Parameter 70 Address Valid to Next Address Valid Address Valid to Output Valid (Random) Chip Enable Low to Wait Valid tCE Chip Enable Low to Output Valid Chip Enable High to Wait Hi-Z tOH tHZ tOE tOLZ tOH tDF tAVADVH tELADVH tADVHAX Chip Enable High to Output Transition Chip Enable High to Output Hi-Z Output Enable Low to Output Valid Output Enable Low to Output Transition Output Enable High to Output Transition Output Enable High to Output Hi-Z Address Valid to Latch Enable High Chip Enable Low to Latch Enable High Latch Enable High to Address Transition Min Max Max Max Max Min Max Max Min Min Max Min Min Min Min Max Min 70 70 11 70 14 0 14 20 0 0 14 7 10 7 7 70 5 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit Read Timings Latch Timings tEHTZ tEHQX(1) tEHQZ(1) tGLQV(2) tGLQX(1) tGHQX(1) tGHQZ(1) tAVLH tELLH tLHAX tLLLH tLLQV tLHGL tADVLADVH Latch Enable Pulse Width tADVLQV tADVHGL Latch Enable Low to Output Valid (Random) Latch Enable High to Output Enable Low 1. Sampled only, not 100% tested. 2. G may be delayed by up to tELQV - tGLQV after the falling edge of E without increasing tELQV. 62/114 BINV(4) VALID VALID VALID NOT VALID ADQ0-ADQ15 VALID ADDRESS VALID VALID VALID NOT VALID VALID M58WR064HU M58WR064HL A16-A21 VALID ADDRESS tAVLH tLLLH L tEHQX tKHQV Note 1 tKHAX tEHEL tKHQX tEHQZ tLLKH tAVKH Figure 10. Synchronous burst read AC waveforms K tELKH E tGLQV tGLQX tGHQX tGHQZ G tELTV Note 2 X Latency tGLTV tKHTV tKHTX Note 2 Valid Data Flow Note 2 Boundary Crossing tEHTZ Hi-Z WAIT Address Latch Standby DC and AC parameters Note 1. The number of clock cycles to be inserted depends on the X latency set in the Configuration Register. 2. The WAIT signal can be configured to be active during wait state or one cycle before. WAIT signal is active Low. 3. Address latched and data output on the rising clock edge. 4. The BINV signal has the waveform shown only if it has been enabled with the Configuration Register. If it is disabled, it remains Low. AI12020b 63/114 64/114 NOT VALID NOT VALID NOT VALID NOT VALID NOT VALID VALID NOT VALID NOT VALID NOT VALID NOT VALID NOT VALID tEHQX tKHQV Note 1 tKHAX tEHEL tEHQZ DC and AC parameters BINV(4) ADQ0-ADQ15 VALID ADDRESS A16-A21 VALID ADDRESS tAVLH tLLLH L tLLKH tAVKH K(3) tELKH Figure 11. Single synchronous read AC waveforms E tGLQX tGLQV tGHQX tGHQZ G tGLTV tKHTV tGHTV tEHTZ tELTV Hi-Z WAIT(2) M58WR064HU M58WR064HL Note 1. The number of clock cycles to be inserted depends on the X latency set in the Configuration Register. 2. The WAIT signal is configured to be active during wait state. WAIT signal is active Low. 3. Address latched and data output on the rising clock edge. 4. The BINV signal has the shown waveform only if it has been enabled with the Configuration Register. When disabled, it remains Low. AI12021b BINV(5) VALID VALID VALID M58WR064HU M58WR064HL ADQ0-ADQ15 VALID VALID VALID VALID ADDRESS VALID A16-A21 VALID ADDRESS tAVLH tLLLH L tEHQX tKHQV Note 1 Note 3 tEHEL tEHQZ tLLKH tAVKH K(4) tELKH tKHAX E tGLQX tGLQV tGHQX tGHQZ Figure 12. Synchronous burst read suspend AC waveforms G tGLTV tEHTZ tELTV Hi-Z WAIT(2) DC and AC parameters Note 1. The number of clock cycles to be inserted depends on the X latency set in the Configuration Register. 2. The WAIT signal is configured to be active during wait state. WAIT signal is active Low. 3. The CLOCK signal can be held high or low 4. Address latched and data output on the rising clock edge. 5. The BINV signal has the shown waveform only if it has been enabled with the Configuration Register. When disabled, it remains Low. 65/114 AI12022b DC and AC parameters Figure 13. Clock input AC Waveform tKHKL M58WR064HU M58WR064HL tKHKH tf tr tKLKH AI06981 Table 23. Symbol tAVKH tELKH tELTV Synchronous Read Timings tEHEL tEHTZ tGHTV tGLTV tKHAX tKHQV tKHTV tKHQX tKHTX tLLKH Clock Specifications Synchronous read AC characteristics M58WR064HU/L Alt tAVCLKH tELCLKH Parameter 70 Address Valid to Clock High Chip Enable Low to Clock High Chip Enable Low to Wait Valid Chip Enable Pulse Width (subsequent synchronous reads) Chip Enable High to Wait Hi-Z Output Enable High to Wait Valid Output Enable Low to Wait Valid tCLKHAX tCLKHQV tCLKHQX Clock High to Address Transition Clock High to Output Valid Clock High to WAIT Valid Clock High to Output Transition Clock High to WAIT Transition Min Min Max Min Max Min Max Min Max Min Min Min Min 5 5 11 14 14 11 11 7 11 3 5 15 3.5 ns ns ns ns ns ns ns ns ns ns ns ns ns Unit tADVLCLKH Latch Enable Low to Clock High tCLK Clock Period (66MHz) Clock High to Clock Low Clock Low to Clock High Clock Fall or Rise Time tKHKH(1) tKHKL tKLKH tf tr Max 3 ns 1. The device can support jitters of +/-5% on clock frequency. 2. Sampled only, not 100% tested. For other timings please refer to Table 22: Asynchronous read AC characteristics. 66/114 PROGRAM OR ERASE VALID tAVAV BANK ADDR. tLHAX tDVWH BANK ADDRESS tAVLH tLLLH VALID ADDRESS VALID ADDRESS tWHDX COMMAND VALID ADDR. CMD OR DATA VALID ADDR. STATUS REGISTER VALID VALID BINV ADQ0-ADQ15 M58WR064HU M58WR064HL A16-A21 L tELLH tWHLL tLHGL E tELWL tWHEH tELQV Figure 14. Write AC waveforms, Write Enable controlled G tGHLL tWLWH tWHWL tWHEL W tWHWPL tWPHWH tQVWPL WP tWHVPL tVPHWH tQVVPL VPP tWHKV K SET-UP COMMAND CONFIRM COMMAND STATUS REGISTER READ 1ST POLLING DC and AC parameters 67/114 AI12023b DC and AC parameters Table 24. Symbol tAVAV tAVLH tDVWH tELLH tELWL Write Enable Controlled Timings tELQV tGHLL tGHWL tLHAX tLHGL tLLLH tWHDX tWHEH tWHEL(2) tWHGL tWHLL tWHWL tWLWH tQVVPL Protection Timings tQVWPL tVPHWH tWHVPL tWHWPL tWPHWH tVPS tDH tCH tCS tDS M58WR064HU M58WR064HL Write AC characteristics, Write Enable controlled M58WR064HU/L Alt tWC Parameter 70 Address Valid to Next Address Valid Address Valid to Latch Enable High Data Valid to Write Enable High Chip Enable Low to Latch Enable High Chip Enable Low to Write Enable Low Chip Enable Low to Output Valid Output Enable High to Latch Enable Low Output Enable High to Write Enable Low Latch Enable High to Address Transition Latch Enable High to Output Enable Low Latch Enable Pulse Width Write Enable High to Input Transition Write Enable High to Chip Enable High Write Enable High to Chip Enable Low Write Enable High to Output Enable Low Write Enable High to Latch Enable Low tWPH Write Enable High to Write Enable Low tWP Write Enable Low to Write Enable High Output (Status Register) Valid to VPP Low Output (Status Register) Valid to Write Protect Low VPP High to Write Enable High Write Enable High to VPP Low Write Enable High to Write Protect Low Write Protect High to Write Enable High Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min 70 7 40 10 0 70 20 20 7 7 7 0 0 25 0 0 25 45 0 0 200 200 200 200 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit 1. Sampled only, not 100% tested. 2. tWHEL has the values shown when reading in the targeted bank or when reading following a Set Configuration Register command. System designers should take this into account and may insert a software No-Op instruction to delay the first read in the same bank after issuing any command and to delay the first read to any address after issuing a Set Configuration Register command. If the first read after the command is a Read Array operation in a different bank and no changes to the Configuration Register have been issued, tWHEL is 0ns. 68/114 PROGRAM OR ERASE VALID tAVAV BANK ADDR. tLHAX BANK ADDRESS tAVLH tLLLH VALID ADDRESS VALID ADDRESS tDVEH tEHDX COMMAND VALID ADDR. CMD OR DATA VALID ADDR. STATUS REGISTER VALID VALID BINV ADQ0-ADQ15 M58WR064HU M58WR064HL A16-A21 L tELLH tEHLL tLHGL E tELEH tWLEL tEHEL tELQV Figure 15. Write AC waveforms, Chip Enable controlled G tGHLL tEHWH tWHEL W tEHWPL tWPHEH tQVWPL WP VPP tVPHEH tEHVPL tQVVPL K tWHKV SET-UP COMMAND CONFIRM COMMAND DC and AC parameters STATUS REGISTER READ 1ST POLLING 69/114 AI12826 DC and AC parameters Table 25. Symbol tAVAV tAVLH tDVEH tEHDX Chip Enable Controlled Timings tEHEL tEHLL tEHWH tELEH tELLH tELQV tGHEL tGHLL tLHAX tLHGL tLLLH tWHEL (1) M58WR064HU M58WR064HL Write AC characteristics, Chip Enable controlled M58WR064HU/L Alt tWC Parameter 70 Address Valid to Next Address Valid Address Valid to Latch Enable High tDS tDH tWPH Data Valid to Chip Enable High Chip Enable High to Input Transition Chip Enable High to Chip Enable Low Chip Enable High to Latch Enable Low tCH tWP Chip Enable High to Write Enable High Chip Enable Low to Chip Enable High Chip Enable Low to Latch Enable High Chip Enable Low to Output Valid Output Enable High to Chip Enable Low Output Enable High to Latch Enable Low Latch Enable High to Address Transition Latch Enable High to Output Enable Low Latch Enable Pulse Width Write Enable High to Chip Enable Low tCS Write Enable Low to Chip Enable Low Chip Enable High to VPP Low Chip Enable High to Write Protect Low Output (Status Register) Valid to VPP Low Output (Status Register) Valid to Write Protect Low tVPS VPP High to Chip Enable High Write Protect High to Chip Enable High Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min 70 7 40 0 25 0 0 45 10 70 20 20 7 7 7 25 0 200 200 0 0 200 200 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit tWLEL tEHVPL Protection Timings 70/114 tEHWPL tQVVPL tQVWPL tVPHEH tWPHEH 1. tWHEL has the values shown when reading in the targeted bank or when reading following a Set Configuration Register command. System designers should take this into account and may insert a software No-Op instruction to delay the first read in the same bank after issuing any command and to delay the first read to any address after issuing a Set Configuration Register command. If the first read after the command is a Read Array operation in a different bank and no changes to the Configuration Register have been issued, tWHEL is 0ns. 3. Sampled only, not 100% tested. M58WR064HU M58WR064HL Figure 16. Reset and Power-up AC waveforms DC and AC parameters W, E, G, L tPHWL tPHEL tPHGL tPHLL tPLWL tPLEL tPLGL tPLLL RP tVDHPH VDD, VDDQ Power-Up Reset AI06976 tPLPH Table 26. Symbol tPLWL tPLEL tPLGL tPLLL tPHWL tPHEL tPHGL tPHLL Reset and Power-up AC characteristics Parameter Reset Low to Write Enable Low, Chip Enable Low, Output Enable Low, Latch Enable Low Reset High to Write Enable Low Chip Enable Low Output Enable Low Latch Enable Low Test Condition During Program During Erase After Power-Down Other Conditions Min Min Min Min 70 10 20 50 80 Unit s s s ns Min 30 ns tPLPH(1)(2) RP Pulse Width tVDHPH(3) Supply Voltages High to Reset High 1. The device Reset is possible but not guaranteed if tPLPH < 50ns. 2. Sampled only, not 100% tested. Min Min 50 50 ns s 3. It is important to assert RP in order to allow proper CPU initialization during Power-Up or Reset. 71/114 Package mechanical M58WR064HU M58WR064HL 15 Package mechanical In order to meet environmental requirements, Numonyx offers these devices in ECOPACK(R) packages. These packages have a Lead-free second-level interconnect. The category of Second-Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. Figure 17. VFBGA44 - 7.7x9mm, 10x4 ball array, 0.5mm pitch, Bottom View Package Outline D D2 D1 FE FE1 SD E1 SE E2 E BALL "A1" FD1 FD e b ddd A A1 A2 BGA-Z47 1. Drawing is not to scale. 72/114 M58WR064HU M58WR064HL Table 27. Package mechanical VFBGA44 - 7.7x9mm, 10x4 ball array, 0.5mm pitch package mechanical data millimeters inches Max 1.00 0.15 0.66 0.32 7.70 4.50 6.50 0.08 9.00 1.50 3.50 0.50 1.60 0.60 3.75 2.75 0.25 0.25 - - - - - - 8.90 9.10 0.354 0.059 0.138 0.020 0.063 0.024 0.148 0.108 0.010 0.010 - - - - - - 0.350 0.27 7.60 0.37 7.80 0.026 0.013 0.303 0.177 0.256 0.003 0.358 0.011 0.299 0.015 0.307 0.006 Typ Min Max 0.039 Symbol Typ A A1 A2 b D D1 D2 ddd E E1 E2 e FD FD1 FE FE1 SD SE Min 73/114 Package mechanical M58WR064HU M58WR064HL Figure 18. VFBGA44 7.5 x 5mm - 10x4 ball array - 0.50mm pitch, package outline D D2 D1 FE FE1 SD E1 SE BALL "A1" E2 E FD1 FD A e b A1 A2 ddd BGA-Z52 1. Drawing is not to scale. 74/114 M58WR064HU M58WR064HL Table 28. Package mechanical VFBGA44 7.5 x 5mm - 10x4 ball array - 0.50mm pitch, package mechanical data millimeters inches Max 1.000 0.150 0.660 0.300 7.500 4.500 6.500 0.080 5.000 1.500 3.500 0.500 1.500 0.500 1.750 0.750 0.250 0.250 - - 4.900 5.100 0.1969 0.0591 0.1378 0.0197 0.0591 0.0197 0.0689 0.0295 0.0098 0.0098 - - 0.1929 0.250 7.400 0.350 7.600 0.0260 0.0118 0.2953 0.1772 0.2559 0.0031 0.2008 0.0098 0.2913 0.0138 0.2992 0.0059 Typ Min Max 0.0394 Symbol Typ A A1 A2 b D D1 D2 ddd E E1 E2 e FD FD1 FE FE1 SD SE Min 75/114 Package mechanical M58WR064HU M58WR064HL Figure 19. VFBGA44 Daisy Chain - Package Connections (Top view through package) AI08181 1 2 3 4 5 6 7 8 9 10 11 12 13 14 G C D 76/114 H A B E F M58WR064HU M58WR064HL Package mechanical Figure 20. VFBGA44 Daisy Chain - PCB connection proposal (top view through package) AI08182 13 14 4 5 6 7 8 9 10 11 1 2 G C D START POINT H A B E F 3 END POINT 12 77/114 Part numbering M58WR064HU M58WR064HL 16 Part numbering Table 29. Example: Device Type M58 Architecture W = Multiple Bank, Burst Mode Operating Voltage R = VDD = VDDQ = 1.7V to 2V Density 064 = 64 Mbit Technology H = 90nm technology Parameter Bank Location U = Top Boot, Multiplexed I/O L = Bottom Boot, Multiplexed I/O Speed 70 = 70ns Package ZB = VFBGA44: 7.7 x 9mm, 0.5mm pitch Temperature Range 6 = -40 to 85C Option E = ECOPACK(R) Package, Standard Packing U = ECOPACK(R) Package, Tape & Reel Packing, 16mm Ordering information scheme M58WR064HU 70 ZB 6 U Devices are shipped from the factory with the memory content bits erased to '1'. For a list of available options (Speed, Package, etc.), for Daisy chain ordering information or for further information on any aspect of this device, please contact the Numonyx Sales Office nearest to you. 78/114 M58WR064HU M58WR064HL Block address tables Appendix A Table 30. Block address tables Top boot block addresses, M58WR064HU # 0 1 2 3 4 Parameter Bank 5 6 7 8 9 10 11 12 13 14 15 16 17 Bank 1 18 19 20 21 22 23 24 25 Bank 2 26 27 28 29 30 Size (KWord) 4 4 4 4 4 4 4 4 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 Address Range 3FF000-3FFFFF 3FE000-3FEFFF 3FD000-3FDFFF 3FC000-3FCFFF 3FB000-3FBFFF 3FA000-3FAFFF 3F9000-3F9FFF 3F8000-3F8FFF 3F0000-3F7FFF 3E8000-3EFFFF 3E0000-3E7FFF 3D8000-3DFFFF 3D0000-3D7FFF 3C8000-3CFFFF 3C0000-3C7FFF 3B8000-3BFFFF 3B0000-3B7FFF 3A8000-3AFFFF 3A0000-3A7FFF 398000-39FFFF 390000-397FFF 388000-38FFFF 380000-387FFF 378000-37FFFF 370000-377FFF 368000-36FFFF 360000-367FFF 358000-35FFFF 350000-357FFF 348000-34FFFF 340000-347FFF Bank(1) 79/114 Block address tables Table 30. M58WR064HU M58WR064HL Top boot block addresses, M58WR064HU (continued) # 31 32 33 Bank 3 34 35 36 37 38 39 40 41 Bank 4 42 43 44 45 46 47 48 49 Bank 5 50 51 52 53 54 55 56 57 Bank 6 58 59 60 61 62 63 64 65 Bank 7 66 67 68 69 70 Size (KWord) 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 Address Range 338000-33FFFF 330000-337FFF 328000-32FFFF 320000-327FFF 318000-31FFFF 310000-317FFF 308000-30FFFF 300000-307FFF 2F8000-2FFFFF 2F0000-2F7FFF 2E8000-2EFFFF 2E0000-2E7FFF 2D8000-2DFFFF 2D0000-2D7FFF 2C8000-2CFFFF 2C0000-2C7FFF 2B8000-2BFFFF 2B0000-2B7FFF 2A8000-2AFFFF 2A0000-2A7FFF 298000-29FFFF 290000-297FFF 288000-28FFFF 280000-287FFF 278000-27FFFF 270000-277FFF 268000-26FFFF 260000-267FFF 258000-25FFFF 250000-257FFF 248000-24FFFF 240000-247FFF 238000-23FFFF 230000-237FFF 228000-22FFFF 220000-227FFF 218000-21FFFF 210000-217FFF 208000-20FFFF 200000-207FFF Bank(1) 80/114 M58WR064HU M58WR064HL Table 30. Block address tables Top boot block addresses, M58WR064HU (continued) # 71 72 73 Bank 8 74 75 76 77 78 79 80 81 Bank 9 82 83 84 85 86 87 88 89 Bank 10 90 91 92 93 94 95 96 97 Bank 11 98 99 100 101 102 103 104 105 Bank 12 106 107 108 109 110 Size (KWord) 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 Address Range 1F8000-1FFFFF 1F0000-1F7FFF 1E8000-1EFFFF 1E0000-1E7FFF 1D8000-1DFFFF 1D0000-1D7FFF 1C8000-1CFFFF 1C0000-1C7FFF 1B8000-1BFFFF 1B0000-1B7FFF 1A8000-1AFFFF 1A0000-1A7FFF 198000-19FFFF 190000-197FFF 188000-18FFFF 180000-187FFF 178000-17FFFF 170000-177FFF 168000-16FFFF 160000-167FFF 158000-15FFFF 150000-157FFF 148000-14FFFF 140000-147FFF 138000-13FFFF 130000-137FFF 128000-12FFFF 120000-127FFF 118000-11FFFF 110000-117FFF 108000-10FFFF 100000-107FFF 0F8000-0FFFFF 0F0000-0F7FFF 0E8000-0EFFFF 0E0000-0E7FFF 0D8000-0DFFFF 0D0000-0D7FFF 0C8000-0CFFFF 0C0000-0C7FFF Bank(1) 81/114 Block address tables Table 30. M58WR064HU M58WR064HL Top boot block addresses, M58WR064HU (continued) # 111 112 113 Bank 13 114 115 116 117 118 119 120 121 Bank 14 122 123 124 125 126 127 128 129 Bank 15 130 131 132 133 134 Size (KWord) 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 Address Range 0B8000-0BFFFF 0B0000-0B7FFF 0A8000-0AFFFF 0A0000-0A7FFF 098000-09FFFF 090000-097FFF 088000-08FFFF 080000-087FFF 078000-07FFFF 070000-077FFF 068000-06FFFF 060000-067FFF 058000-05FFFF 050000-057FFF 048000-04FFFF 040000-047FFF 038000-03FFFF 030000-037FFF 028000-02FFFF 020000-027FFF 018000-01FFFF 010000-017FFF 008000-00FFFF 000000-007FFF Bank(1) 1. There are two Bank Regions: Bank Region 1 contains all the banks that are made up of main blocks only; Bank Region 2 contains the banks that are made up of the parameter and main blocks (Parameter Bank). Table 31. Bottom boot block addresses, M58WR064HL # 134 133 132 Bank 15 131 130 129 128 127 Size (KWord) 32 32 32 32 32 32 32 32 Address Range 3F8000-3FFFFF 3F0000-3F7FFF 3E8000-3EFFFF 3E0000-3E7FFF 3D8000-3DFFFF 3D0000-3D7FFF 3C8000-3CFFFF 3C0000-3C7FFF Bank(1) 82/114 M58WR064HU M58WR064HL Table 31. Block address tables Bottom boot block addresses, M58WR064HL (continued) # 126 125 124 Bank 14 123 122 121 120 119 118 117 116 Bank 13 115 114 113 112 111 110 109 108 Bank 12 107 106 105 104 103 102 101 100 Bank 11 99 98 97 96 95 Size (KWord) 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 Address Range 3B8000-3BFFFF 3B0000-3B7FFF 3A8000-3AFFFF 3A0000-3A7FFF 398000-39FFFF 390000-397FFF 388000-38FFFF 380000-387FFF 378000-37FFFF 370000-377FFF 368000-36FFFF 360000-367FFF 358000-35FFFF 350000-357FFF 348000-34FFFF 340000-347FFF 338000-33FFFF 330000-337FFF 328000-32FFFF 320000-327FFF 318000-31FFFF 310000-317FFF 308000-30FFFF 300000-307FFF 2F8000-2FFFFF 2F0000-2F7FFF 2E8000-2EFFFF 2E0000-2E7FFF 2D8000-2DFFFF 2D0000-2D7FFF 2C8000-2CFFFF 2C0000-2C7FFF Bank(1) 83/114 Block address tables Table 31. M58WR064HU M58WR064HL Bottom boot block addresses, M58WR064HL (continued) # 94 93 92 Bank 10 91 90 89 88 87 86 85 84 Bank 9 83 82 81 80 79 78 77 76 Bank 8 75 74 73 72 71 70 69 68 Bank 7 67 66 65 64 63 Size (KWord) 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 Address Range 2B8000-2BFFFF 2B0000-2B7FFF 2A8000-2AFFFF 2A0000-2A7FFF 298000-29FFFF 290000-297FFF 288000-28FFFF 280000-287FFF 278000-27FFFF 270000-277FFF 268000-26FFFF 260000-267FFF 258000-25FFFF 250000-257FFF 248000-24FFFF 240000-247FFF 238000-23FFFF 230000-237FFF 228000-22FFFF 220000-227FFF 218000-21FFFF 210000-217FFF 208000-20FFFF 200000-207FFF 1F8000-1FFFFF 1F0000-1F7FFF 1E8000-1EFFFF 1E0000-1E7FFF 1D8000-1DFFFF 1D0000-1D7FFF 1C8000-1CFFFF 1C0000-1C7FFF Bank(1) 84/114 M58WR064HU M58WR064HL Table 31. Block address tables Bottom boot block addresses, M58WR064HL (continued) # 62 61 60 Bank 6 59 58 57 56 55 54 53 52 Bank 5 51 50 49 48 47 46 45 44 Bank 4 43 42 41 40 39 38 37 36 Bank 3 35 34 33 32 31 Size (KWord) 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 Address Range 1B8000-1BFFFF 1B0000-1B7FFF 1A8000-1AFFFF 1A0000-1A7FFF 198000-19FFFF 190000-197FFF 188000-18FFFF 180000-187FFF 178000-17FFFF 170000-177FFF 168000-16FFFF 160000-167FFF 158000-15FFFF 150000-157FFF 148000-14FFFF 140000-147FFF 138000-13FFFF 130000-137FFF 128000-12FFFF 120000-127FFF 118000-11FFFF 110000-117FFF 108000-10FFFF 100000-107FFF 0F8000-0FFFFF 0F0000-0F7FFF 0E8000-0EFFFF 0E0000-0E7FFF 0D8000-0DFFFF 0D0000-0D7FFF 0C8000-0CFFFF 0C0000-0C7FFF Bank(1) 85/114 Block address tables Table 31. M58WR064HU M58WR064HL Bottom boot block addresses, M58WR064HL (continued) # 30 29 28 Bank 2 27 26 25 24 23 22 21 20 Bank 1 19 18 17 16 15 14 13 12 11 10 Parameter Bank 9 8 7 6 5 4 3 2 1 0 Size (KWord) 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 4 4 4 4 4 4 4 4 Address Range 0B8000-0BFFFF 0B0000-0B7FFF 0A8000-0AFFFF 0A0000-0A7FFF 098000-09FFFF 090000-097FFF 088000-08FFFF 080000-087FFF 078000-07FFFF 070000-077FFF 068000-06FFFF 060000-067FFF 058000-05FFFF 050000-057FFF 048000-04FFFF 040000-047FFF 038000-03FFFF 030000-037FFF 028000-02FFFF 020000-027FFF 018000-01FFFF 010000-017FFF 008000-00FFFF 007000-007FFF 006000-006FFF 005000-005FFF 004000-004FFF 003000-003FFF 002000-002FFF 001000-001FFF 000000-000FFF Bank(1) 1. There are two Bank Regions: Bank Region 2 contains all the banks that are made up of main blocks only; Bank Region 1 contains the banks that are made up of the parameter and main blocks (Parameter Bank). 86/114 M58WR064HU M58WR064HL Common Flash Interface Appendix B Common Flash Interface The Common Flash Interface is a JEDEC approved, standardized data structure that can be read from the Flash memory device. It allows a system software to query the device to determine various electrical and timing parameters, density information and functions supported by the memory. The system can interface easily with the device, enabling the software to upgrade itself when necessary. When the Read CFI Query Command is issued the device enters CFI Query mode and the data structure is read from the memory. Tables 32, 33, 34, 35, 36, 37, 38, 39, 40 and 41 show the addresses used to retrieve the data. The Query data is always presented on the lowest order data outputs (DQ0-DQ7), the other outputs (DQ8-DQ15) are set to 0. The CFI data structure also contains a security area where a 64 bit unique security number is written (see Figure 4: Protection Register memory map). This area can be accessed only in Read mode by the final user. It is impossible to change the security number after it has been written by Numonyx. Issue a Read Array command to return to Read mode. Table 32. Offset 00h 10h 1Bh 27h P A Reserved CFI Query Identification String System Interface Information Device Geometry Definition Primary Algorithm-specific Extended Query table Alternate Algorithm-specific Extended Query table Security Code Area Query structure overview(1) Sub-section Name Description Reserved for algorithm-specific information Command set ID and algorithm data offset Device timing & voltage information Flash device layout Additional information specific to the Primary Algorithm (optional) Additional information specific to the Alternate Algorithm (optional) Lock Protection Register Unique device Number and User Programmable OTP 80h 1. The Flash memory display the CFI data structure when CFI Query command is issued. In this table are listed the main sub-sections detailed in Tables 33, 34, 35 and 36. Query data is always presented on the lowest order data outputs. 87/114 Common Flash Interface Table 33. Offset 00h 01h 02h 03h 04h-0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah M58WR064HU M58WR064HL CFI Query Identification String Sub-section Name 0020h 88C0h 88C1h reserved DRC reserved 0051h 0052h 0059h 0003h 0000h Primary Algorithm Command Set and Control Interface ID code 16 bit ID code defining a specific algorithm p = 39h Query Unique ASCII String "QRY" Manufacturer Code Device Code Reserved Die Revision Code Reserved "Q" "R" "Y" M58WR064HU M58WR064HL Description Value Numony x Top Bottom offset = P = 0039h Address for Primary Algorithm extended Query table (see Table 35) 0000h 0000h 0000h value = A = 0000h Address for Alternate Algorithm extended Query table 0000h Alternate Vendor Command Set and Control Interface ID Code second vendor - specified algorithm supported NA NA 88/114 M58WR064HU M58WR064HL Table 34. Offset Common Flash Interface CFI Query system interface information Data Description VDD Logic Supply Minimum Program/Erase or Write voltage bit 7 to 4 BCD value in volts bit 3 to 0 BCD value in 100 millivolts VDD Logic Supply Maximum Program/Erase or Write voltage bit 7 to 4 BCD value in volts bit 3 to 0 BCD value in 100 millivolts VPP [Programming] Supply Minimum Program/Erase voltage bit 7 to 4 HEX value in volts bit 3 to 0 BCD value in 100 millivolts VPP [Programming] Supply Maximum Program/Erase voltage bit 7 to 4 HEX value in volts bit 3 to 0 BCD value in 100 millivolts Typical time-out per single byte/word program = 2n s Typical time-out for multi-Byte programming = 2 s Typical time-out per individual block erase = Typical time-out for full chip erase = 2n ms Maximum time-out for word program = 2 times typical Maximum time-out for multi-Byte programming = 2n n n n Value 1Bh 0017h 1.7V 1Ch 0020h 2V 1Dh 00B4h 11.4V 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h 00C6h 0004h 0000h 000Ah 0000h 0003h 0000h 0002h 0000h 12.6V 16s NA 1s NA 128s NA 4s NA 2n ms times typical Maximum time-out per individual block erase = 2 times typical Maximum time-out for chip erase = 2n times typical 89/114 Common Flash Interface Table 35. Offset Word Mode 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh M58WR064HU 2Fh 30h 31h 32h 33h 34h 35h 38h 2Dh 2Eh M58WR064HL 2Fh 30h 31h 32h 33h 34h 35h 38h M58WR064HU M58WR064HL Device geometry definition Data 0017h 0001h 0000h 0000h 0000h 0002h 007Eh 0000h 0000h 0001h 0007h 0000h 0020h 0000h Description Device Size = 2n in number of bytes Flash Device Interface Code description Maximum number of bytes in multi-byte program or page = 2n Number of identical sized erase block regions within the device bit 7 to 0 = x = number of Erase Block Regions Region 1 Information Number of identical-size erase blocks = 007Eh+1 Region 1 Information Block size in Region 1 = 0100h * 256 byte Region 2 Information Number of identical-size erase blocks = 0007h+1 Region 2 Information Block size in Region 2 = 0020h * 256 byte Value 8 MBytes x16 Async. NA 2 127 64 KByte 8 8 KByte NA 8 8 KByte 127 64 KByte NA Reserved for future erase block region information 0007h 0000h 0020h 0000h 007Eh 0000h 0000h 0001h Region 1 Information Number of identical-size erase block = 0007h+1 Region 1 Information Block size in Region 1 = 0020h * 256 byte Region 2 Information Number of identical-size erase block = 007Eh+1 Region 2 Information Block size in Region 2 = 0100h * 256 byte Reserved for future erase block region information 90/114 M58WR064HU M58WR064HL Table 36. Offset (P)h = 39h Common Flash Interface Primary algorithm-specific extended query table Data 0050h 0052h 0049h Primary Algorithm extended Query table unique ASCII string "PRI" Description Value "P" "R" "I" Major version number, ASCII Minor version number, ASCII "1" "3" (P+3)h = 3Ch (P+4)h = 3Dh (P+5)h = 3Eh 0031h 0033h (P+7)h = 40h (P+8)h = 41h 00E6h Extended Query table contents for Primary Algorithm. Address (P+5)h contains less significant byte. 0003h bit 0 Chip Erase supported (1 = Yes, 0 = No) 0000h bit 1 Erase Suspend supported (1 = Yes, 0 = No) bit 2 Program Suspend supported (1 = Yes, 0 = No) bit 3 Legacy Lock/Unlock supported (1 = Yes, 0 = No) bit 4 Queued Erase supported (1 = Yes, 0 = No) bit 5 Instant individual block locking supported (1 = Yes, 0 = No) bit 6 Protection bits supported (1 = Yes, 0 = No) bit 7 Page mode read supported (1 = Yes, 0 = No) 0000h bit 8 Synchronous read supported (1 = Yes, 0 = No) bit 9 Simultaneous operation supported (1 = Yes, 0 = No) bit 10 to 31 Reserved; undefined bits are `0'. If bit 31 is '1' then another 31 bit field of optional features follows at the end of the bit-30 field. Supported Functions after Suspend Read Array, Read Status Register and CFI Query bit 0 Program supported after Erase Suspend (1 = Yes, 0 = No) bit 7 to 1 Reserved; undefined bits are `0' Block Protect Status Defines which bits in the Block Status Register section of the Query are implemented. bit 0 Block protect Status Register Lock/Unlock bit active(1 = Yes, 0 = No) bit 1 Block Lock Status Register Lock-Down bit active (1 = Yes, 0 = No) bit 15 to 2 Reserved for future use; undefined bits are `0' VDD Logic Supply Optimum Program/Erase voltage (highest performance) No Yes Yes No No Yes Yes Yes Yes Yes (P+9)h = 42h 0001h Yes (P+A)h = 43h 0003h (P+B)h = 44h 0000h Yes Yes (P+C)h = 45h 0018h bit 7 to 4 HEX value in volts bit 3 to 0 BCD value in 100 mV VPP Supply Optimum Program/Erase voltage 1.8V (P+D)h = 46h 00C0h bit 7 to 4 HEX value in volts bit 3 to 0 BCD value in 100 mV 12V 91/114 Common Flash Interface Table 37. Offset (P+E)h = 47h (P+F)h = 48h (P+10)h = 49h (P+11)h = 4Ah (P+12)h= 4Bh M58WR064HU M58WR064HL Protection Register information Data 0001h 0080h 0000h 0003h 0004h Description Number of protection register fields in JEDEC ID space. 0000h indicates that 256 fields are available. Protection Field 1: Protection Description Bits 0-7 Lower byte of protection register address Bits 8-15 Upper byte of protection register address Bits 16-23 2n bytes in factory pre-programmed region Bits 24-31 2n bytes in user programmable region Value 1 0080h 8 Bytes 16 Bytes Table 38. Offset Burst read information Data Description Page-mode read capability bits 0-7'n' such that 2n HEX value represents the number of read-page bytes. See offset 28h for device word width to determine page-mode data output width. Number of synchronous mode read configuration fields that follow. Synchronous mode read capability configuration 1 bit 3-7 Reserved bit 0-2 'n' such that 2n+1 HEX value represents the maximum number of continuous synchronous reads when the device is configured for its maximum word width. A value of 07h indicates that the device is capable of continuous linear bursts that will output data until the internal burst counter reaches the end of the device's burstable address space. This field's 3-bit value can be written directly to the read configuration register bit 0-2 if the device is configured for its maximum word width. See offset 28h for word width to determine the burst data output width. Synchronous mode read capability configuration 2 Synchronous mode read capability configuration 3 Synchronous mode read capability configuration 4 Value (P+13)h = 4Ch 0003h 8 Bytes (P+14)h = 4Dh 0004h 4 (P+15)h = 4Eh 0001h 4 (P+16)h = 4Fh (P+17)h = 50h (P+18)h = 51h 0002h 0003h 0007h 8 16 Cont. Table 39. Bank and erase block region information(1) (2) M58WR064HL Description Offset (P+19)h = 52h Data 02h Number of Bank Regions within the device M58WR064HU Offset (P+19)h = 52h Data 02h 1. The variable P is a pointer which is defined at CFI offset 15h. 2. Bank Regions. There are two Bank Regions, see Appendix A, Table 30 and Table 31 92/114 M58WR064HU M58WR064HL Table 40. Bank and erase block region 1 information(1) M58WR064HL Common Flash Interface M58WR064HU Offset Data Description Offset (P+1A)h = 53h (P+1B)h = 54h Data 01h Number of identical banks within Bank Region 1 (P+1B)h = 54h 00h 00h Number of program or erase operations allowed in Bank Region 1: Bits 0-3: Number of simultaneous program operations Bits 4-7: Number of simultaneous erase operations Number of program or erase operations allowed in other banks while a bank in same region is programming Bits 0-3: Number of simultaneous program operations Bits 4-7: Number of simultaneous erase operations Number of program or erase operations allowed in other banks while a bank in this region is erasing Bits 0-3: Number of simultaneous program operations Bits 4-7: Number of simultaneous erase operations Types of erase block regions in Bank Region 1 n = number of erase block regions with contiguous same-size erase blocks. Symmetrically blocked banks have one blocking region.(2) Bank Region 1 Erase Block Type 1 Information Bits 0-15: n+1 = number of identical-sized erase blocks Bits 16-31: nx256 = number of bytes in erase block region Bank Region 1 (Erase Block Type 1) Minimum block erase cycles x 1000 Bank Region 1 (Erase Block Type 1): BIts per cell, internal ECC Bits 0-3: bits per cell in erase region Bit 4: reserved for "internal ECC used" BIts 5-7: reserved 5Eh 01 5Eh 01 Bank Region 1 (Erase Block Type 1): Page mode and synchronous mode capabilities Bit 0: Page-mode reads permitted Bit 1: Synchronous reads permitted Bit 2: Synchronous writes permitted Bits 3-7: reserved (P+1A)h = 53h 0Fh (P+1C)h = 55h 11h (P+1C)h = 55h 11h (P+1D)h = 56h 00h (P+1D)h = 56h 00h (P+1E)h = 57h 00h (P+1E)h = 57h 00h (P+1F)h = 58h 01h (P+1F)h = 58h 02h (P+20)h = 59h 07h (P+20)h = 59h (P+21)h = 5Ah (P+22)h = 5Bh (P+23)h = 5Ch (P+24)h = 5Dh (P+25)h = 5Eh 07h 00h 20h 00h 64h 00h (P+21)h = 5Ah 00h (P+22)h = 5Bh 00h (P+23)h = 5Ch 01h (P+24)h = 5Dh 64h (P+25)h = 5Eh 00h (P+26)h = 5Fh 01h (P+26)h = 5Fh 01h (P+27)h = 60h 03h (P+27)h = 60h 03h 93/114 Common Flash Interface Table 40. M58WR064HU M58WR064HL Bank and erase block region 1 information(1) (continued) M58WR064HL Description Offset (P+28)h = 61h (P+29)h = 62h (P+2A)h = 63h (P+2B)h = 64h (P+2C)h = 65h (P+2D)h = 66h Data 06h 00h 00h 01h 64h 00h Bank Region 1 Erase Block Type 2 Information M58WR064HU Offset Data Bits 0-15: n+1 = number of identical-sized erase blocks Bits 16-31: nx256 = number of bytes in erase block region Bank Region 1 (Erase Block Type 2) Minimum block erase cycles x 1000 Bank Regions 1 (Erase Block Type 2): BIts per cell, internal ECC Bits 0-3: bits per cell in erase region Bit 4: reserved for "internal ECC used" BIts 5-7: reserved Bank Region 1 (Erase Block Type 2): Page mode and synchronous mode capabilities Bit 0: Page-mode reads permitted Bit 1: Synchronous reads permitted Bit 2: Synchronous writes permitted Bits 3-7: reserved (P+2E)h = 67h 01h (P+2F)h = 68h 03h 1. The variable P is a pointer which is defined at CFI offset 15h. 2. Bank Regions. There are two Bank Regions, see Appendix A, Table 30 and Table 31. 94/114 M58WR064HU M58WR064HL Table 41. Bank and erase block region 2 information(1) M58WR064HL Common Flash Interface M58WR064HU Offset Data Description Offset Data Number of identical banks within Bank Region 2 (P+29)h = 62h 00h (P+31)h = 6Ah 00h Number of program or erase operations allowed in Bank Region 2: (P+2A)h = 63h 11h (P+32)h = 6Bh 11h Bits 0-3: Number of simultaneous program operations Bits 4-7: Number of simultaneous erase operations Number of program or erase operations allowed in other banks while a bank in this region is programming (P+2B)h = 64h 00h (P+33)h = 6Ch 00h Bits 0-3: Number of simultaneous program operations Bits 4-7: Number of simultaneous erase operations Number of program or erase operations allowed in other banks while a bank in this region is erasing (P+2C)h = 65h 00h (P+34)h = 6Dh 00h Bits 0-3: Number of simultaneous program operations Bits 4-7: Number of simultaneous erase operations Types of erase block regions in Bank Region 2 n = number of erase block regions with contiguous same(P+2D)h = 66h 02h (P+35)h = 6Eh 01h size erase blocks. Symmetrically blocked banks have one blocking region.(2) (P+2E)h = 67h 06h (P+36)h = 6Fh 07h Bank Region 2 Erase Block Type 1 Information (P+2F)h = 68h 00h (P+37)h = 70h 00h Bits 0-15: n+1 = number of identical-sized erase blocks (P+30)h = 69h 00h (P+38)h = 71h 00h Bits 16-31: nx256 = number of bytes in erase block region (P+31)h = 6Ah 01h (P+39)h = 72h 01h (P+28)h = 61h 01h (P+30)h = 69h 0Fh (P+32)h = 6Bh 64h (P+3A)h = 73h 64h Bank Region 2 (Erase Block Type 1) (P+33)h = 6Ch 00h (P+3B)h = 74h 00h Minimum block erase cycles x 1000 Bank Region 2 (Erase Block Type 1): BIts per cell, internal ECC (P+34)h = 6Dh 01h (P+3C)h = 75h 01h Bits 0-3: bits per cell in erase region Bit 4: reserved for "internal ECC used" BIts 5-7: reserved Bank Region 2 (Erase Block Type 1): Page mode and synchronous mode capabilities (defined in Table 38) Bit 0: Page-mode reads permitted (P+35)h = 6Eh 03h (P+3D)h = 76h 03h Bit 1: Synchronous reads permitted Bit 2: Synchronous writes permitted Bits 3-7: reserved (P+36)h = 6Fh 07h (P+37)h = 70h 00h (P+38)h = 71h 20h (P+39)h = 72h 00h Bank Region 2 Erase Block Type 2 Information Bits 0-15: n+1 = number of identical-sized erase blocks Bits 16-31: nx256 = number of bytes in erase block region 95/114 Common Flash Interface Table 41. M58WR064HU M58WR064HL Bank and erase block region 2 information(1) (continued) M58WR064HL Description Offset Data Bank Region 2 (Erase Block Type 2) Minimum block erase cycles x 1000 Bank Region 2 (Erase Block Type 2): BIts per cell, internal ECC Bits 0-3: bits per cell in erase region Bit 4: reserved for "internal ECC used" BIts 5-7: reserved Bank Region 2 (Erase Block Type 2): Page mode and synchronous mode capabilities (defined in Table 38) Bit 0: Page-mode reads permitted Bit 1: Synchronous reads permitted Bit 2: Synchronous writes permitted Bits 3-7: reserved (P+3E)h = 77h (P+3F)h = 78h Feature Space definitions Reserved M58WR064HU Offset Data (P+3A)h = 73h 64h (P+3B)h = 74h 00h (P+3C)h = 75h 01h (P+3D)h = 76h 03h (P+3E)h = 77h (P+3F)h = 78h 1. The variable P is a pointer which is defined at CFI offset 15h. 2. Bank Regions. There are two Bank Regions, see Appendix A, Table 30 and Table 31. 96/114 M58WR064HU M58WR064HL Flowcharts and pseudo codes Appendix C Flowcharts and pseudo codes Figure 21. Program flowchart and pseudo code Start program_command (addressToProgram, dataToProgram) {: Write 40h or 10h (3) writeToFlash (addressToProgram, 0x40); /*writeToFlash (addressToProgram, 0x10);*/ /*see note (3)*/ writeToFlash (addressToProgram, dataToProgram) ; /*Memory enters read status state after the Program Command*/ do { status_register=readFlash (addressToProgram); "see note (3)"; /* E or G must be toggled*/ NO } while (status_register.SR7== 0) ; YES SR3 = 0 YES SR4 = 0 YES SR1 = 0 YES End } NO Program to Protected Block Error (1, 2) if (status_register.SR1==1) /*program to protect block error */ error_handler ( ) ; NO Program Error (1, 2) if (status_register.SR4==1) /*program error */ error_handler ( ) ; NO VPP Invalid Error (1, 2) if (status_register.SR3==1) /*VPP invalid error */ error_handler ( ) ; Write Address & Data Read Status Register (3) SR7 = 1 AI06170c 1. Status check of SR1 (Protected Block), SR3 (VPP Invalid) and SR4 (Program Error) can be made after each program operation or after a sequence. 2. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations. 3. Any address within the bank can equally be used. 97/114 Flowcharts and pseudo codes Figure 22. Double Word Program flowchart and pseudo code M58WR064HU M58WR064HL Start Write 35h Write Address 1 & Data 1 (3, 4) Write Address 2 & Data 2 (3) double_word_program_command (addressToProgram1, dataToProgram1, addressToProgram2, dataToProgram2) { writeToFlash (addressToProgram1, 0x35); /*see note (4)*/ writeToFlash (addressToProgram1, dataToProgram1) ; /*see note (3) */ writeToFlash (addressToProgram2, dataToProgram2) ; /*see note (3) */ /*Memory enters read status state after the Program command*/ do { status_register=readFlash (addressToProgram) ; "see note (4)" /* E or G must be toggled*/ Read Status Register (4) SR7 = 1 YES SR3 = 0 YES SR4 = 0 YES SR1 = 0 YES End NO } while (status_register.SR7== 0) ; NO VPP Invalid Error (1, 2) if (status_register.SR3==1) /*VPP invalid error */ error_handler ( ) ; NO Program Error (1, 2) if (status_register.SR4==1) /*program error */ error_handler ( ) ; NO Program to Protected Block Error (1, 2) if (status_register.SR1==1) /*program to protect block error */ error_handler ( ) ; } AI06171b 1. Status check of b1 (Protected Block), b3 (VPP Invalid) and b4 (Program Error) can be made after each program operation or after a sequence. 2. If an error is found, the Status Register must be cleared before further Program/Erase operations. 3. Address 1 and Address 2 must be consecutive addresses differing only for bit A0. 4. Any address within the bank can equally be used. 98/114 M58WR064HU M58WR064HL Figure 23. Quadruple Word Program flowchart and pseudo code Start Flowcharts and pseudo codes Write 56h Write Address 1 & Data 1 (3, 4) quadruple_word_program_command (addressToProgram1, dataToProgram1, addressToProgram2, dataToProgram2, addressToProgram3, dataToProgram3, addressToProgram4, dataToProgram4) { writeToFlash (addressToProgram1, 0x56); /*see note (4) */ writeToFlash (addressToProgram1, dataToProgram1) ; /*see note (3) */ writeToFlash (addressToProgram2, dataToProgram2) ; /*see note (3) */ writeToFlash (addressToProgram3, dataToProgram3) ; /*see note (3) */ writeToFlash (addressToProgram4, dataToProgram4) ; /*see note (3) */ /*Memory enters read status state after the Program command*/ do { status_register=readFlash (addressToProgram) ; /"see note (4) "/ /* E or G must be toggled*/ Write Address 2 & Data 2 (3) Write Address 3 & Data 3 (3) Write Address 4 & Data 4 (3) Read Status Register (4) SR7 = 1 YES SR3 = 0 YES SR4 = 0 YES SR1 = 0 YES End NO } while (status_register.SR7== 0) ; NO VPP Invalid Error (1, 2) if (status_register.SR3==1) /*VPP invalid error */ error_handler ( ) ; NO Program Error (1, 2) if (status_register.SR4==1) /*program error */ error_handler ( ) ; NO Program to Protected Block Error (1, 2) if (status_register.SR==1) /*program to protect block error */ error_handler ( ) ; } AI06977b 1. Status check of SR1 (Protected Block), SR3 (VPP Invalid) and SR4 (Program Error) can be made after each program operation or after a sequence. 2. If an error is found, the Status Register must be cleared before further Program/Erase operations. 3. Address 1 to Address 4 must be consecutive addresses differing only for bits A0 and A1. 4. Any address within the bank can equally be used. 99/114 Flowcharts and pseudo codes M58WR064HU M58WR064HL Figure 24. Program Suspend & Resume flowchart and pseudo code Start program_suspend_command ( ) { writeToFlash (any_address, 0xB0) ; writeToFlash (bank_address, 0x70) ; /* read status register to check if program has already completed */ Write 70h do { status_register=readFlash (bank_address) ; /* E or G must be toggled*/ Write B0h Read Status Register SR7 = 1 YES SR2 = 1 NO } while (status_register.SR7== 0) ; NO Program Complete if (status_register.SR2==0) /*program completed */ { writeToFlash (bank_address, 0xFF) ; read_data ( ) ; /*The device returns to Read Array (as if program/erase suspend was not issued).*/ } else { writeToFlash (bank_address, 0xFF) ; Write FFh YES Write FFh Read Data Read data from another address read_data ( ); /*read data from another address*/ Write D0h writeToFlash (any_address, 0xD0) ; /*write 0xD0 to resume program*/ Write 70h(1) } Program Continues with Bank in Read Status Register Mode } writeToFlash (bank_address, 0x70) ; /*read status register to check if program has completed */ AI10117b 1. The Read Status Register command (Write 70h) can be issued just before or just after the Program Resume command. 100/114 M58WR064HU M58WR064HL Figure 25. Block Erase flowchart and pseudo code Flowcharts and pseudo codes Start erase_command ( blockToErase ) { writeToFlash (blockToErase, 0x20) ; /*see note (2) */ writeToFlash (blockToErase, 0xD0) ; /* only ADQ12-ADQ15 and A16-A21 significant */ /* Memory enters read status state after the Erase Command */ do { status_register=readFlash (blockToErase) ; /* see note (2) */ /* E or G must be toggled*/ Write 20h (2) Write Block Address & D0h Read Status Register (2) SR7 = 1 NO } while (status_register.SR7== 0) ; YES SR3 = 0 YES SR4, SR5 = 1 NO SR5 = 0 YES SR1 = 0 YES End } NO Erase to Protected Block Error (1) if (status_register.SR1==1) /*program to protect block error */ error_handler ( ) ; NO Erase Error (1) if ( (status_register.SR5==1) ) /* erase error */ error_handler ( ) ; YES Command Sequence Error (1) if ( (status_register.SR4==1) && (status_register.SR5==1) ) /* command sequence error */ error_handler ( ) ; NO VPP Invalid Error (1) if (status_register.SR3==1) /*VPP invalid error */ error_handler ( ) ; AI10567b 1. If an error is found, the Status Register must be cleared before further Program/Erase operations. 2. Any address within the bank can equally be used. 101/114 Flowcharts and pseudo codes Figure 26. Erase Suspend & Resume flowchart and pseudo code M58WR064HU M58WR064HL Start Write B0h erase_suspend_command ( ) { writeToFlash (bank_address, 0xB0) ; writeToFlash (bank_address, 0x70) ; /* read status register to check if erase has already completed */ Write 70h Read Status Register do { status_register=readFlash (bank_address) ; /* E or G must be toggled*/ SR7 = 1 YES SR6 = 1 NO } while (status_register.SR7== 0) ; NO Erase Complete if (status_register.SR6==0) /*erase completed */ { writeToFlash (bank_address, 0xFF) ; Write FFh Read Data YES Write FFh Read data from another block or Program/Protection Register Program or Block Lock/Unlock/Lock-Down Write D0h else } read_data ( ) ; /*The device returns to Read Array (as if program/erase suspend was not issued).*/ { writeToFlash (bank_address, 0xFF) ; read_program_data ( ); /*read or program data from another block*/ writeToFlash (bank_address, 0xD0) ; /*write 0xD0 to resume erase*/ writeToFlash (bank_address, 0x70) ; /*read status register to check if erase has completed */ } } Write 70h(1) Erase Continues with Bank in Read Status Register Mode AI10116b 1. The Read Status Register command (Write 70h) can be issued just before or just after the Erase Resume command. 102/114 M58WR064HU M58WR064HL Figure 27. Locking Operations flowchart and pseudo code Flowcharts and pseudo codes Start Write 60h (1) locking_operation_command (address, lock_operation) { writeToFlash (address, 0x60) ; /*configuration setup*/ /* see note (1) */ if (lock_operation==LOCK) /*to protect the block*/ writeToFlash (address, 0x01) ; else if (lock_operation==UNLOCK) /*to unprotect the block*/ writeToFlash (address, 0xD0) ; else if (lock_operation==LOCK-DOWN) /*to lock the block*/ writeToFlash (address, 0x2F) ; writeToFlash (address, 0x90) ; /*see note (1) */ Write 01h, D0h or 2Fh Write 90h (1) Read Block Lock States Locking change confirmed? YES Write FFh (1) NO if (readFlash (address) ! = locking_state_expected) error_handler () ; /*Check the locking state (see Read Block Signature table )*/ writeToFlash (address, 0xFF) ; /*Reset to Read Array mode*/ /*see note (1) */ } End AI06176b 1. Any address within the bank can equally be used. 103/114 Flowcharts and pseudo codes Figure 28. Protection Register Program flowchart and pseudo code M58WR064HU M58WR064HL Start Write C0h (3) protection_register_program_command (addressToProgram, dataToProgram) {: writeToFlash (addressToProgram, 0xC0) ; /*see note (3) */ writeToFlash (addressToProgram, dataToProgram) ; /*Memory enters read status state after the Program Command*/ do { status_register=readFlash (addressToProgram) ; /* see note (3) */ /* E or G must be toggled*/ NO } while (status_register.SR7== 0) ; Write Address & Data Read Status Register (3) SR7 = 1 YES SR3 = 0 YES SR4 = 0 YES SR1 = 0 YES End NO VPP Invalid Error (1, 2) if (status_register.SR3==1) /*VPP invalid error */ error_handler ( ) ; NO Program Error (1, 2) if (status_register.SR4==1) /*program error */ error_handler ( ) ; NO Program to Protected Block Error (1, 2) if (status_register.SR1==1) /*program to protect block error */ error_handler ( ) ; } AI06177b 1. Status check of SR1 (Protected Block), SR3 (VPP Invalid) and SR4 (Program Error) can be made after each program operation or after a sequence. 2. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations. 3. Any address within the bank can equally be used. 104/114 M58WR064HU M58WR064HL Figure 29. Enhanced Factory Program flowchart SETUP PHASE Start Write 30h Address WA1 Write D0h Address WA1 Flowcharts and pseudo codes VERIFY PHASE Write PD1 Address WA1(1) Read Status Register Read Status Register SR0 = 0? NO SR7 = 0? YES Write PD2 Address WA2(1) NO NO Check SR4, SR3 and SR1 for program, VPP and Lock Errors Exit PROGRAM PHASE YES SR0 = 0? YES Write PD1 Address WA1 Read Status Register Read Status Register SR0 = 0? YES NO Write PDn Address WAn(1) NO SR0 = 0? YES Write PD2 Address WA2(1) Read Status Register Read Status Register NO SR0 = 0? YES SR0 = 0? YES Write PDn Address WAn(1) NO Write FFFFh Address = Block WA1 / EXIT PHASE Read Status Register Read Status Register SR7 = 1? YES NO SR0 = 0? YES Write FFFFh Address = Block WA1 / NO Check Status Register for Errors End AI06160 1. Address can remain Starting Address WA1 or be incremented. 105/114 Flowcharts and pseudo codes M58WR064HU M58WR064HL 16.1 Enhanced factory program pseudo code efp_command(addressFlow,dataFlow,n) /* n is the number of data to be programmed */ { /* setup phase */ writeToFlash(addressFlow[0],0x30); writeToFlash(addressFlow[0],0xD0); status_register=readFlash(any_address); if (status_register.SR7==1){ /*EFP aborted for an error*/ if (status_register.SR4==1) /*program error*/ error_handler(); if (status_register.SR3==1) /*VPP invalid error*/ error_handler(); if (status_register.SR1==1) /*program to protect block error*/ error_handler(); } else{ /*Program Phase*/ do{ status_register=readFlash(any_address); /* E or G must be toggled*/ } while (status_register.SR0==1) /*Ready for first data*/ for (i=0; i++; i< n){ writeToFlash(addressFlow[i],dataFlow[i]); /* status register polling*/ do{ status_register=readFlash(any_address); /* E or G must be toggled*/ } while (status_register.SR0==1); /* Ready for a new data */ } writeToFlash(another_block_address,FFFFh); /* Verify Phase */ for (i=0; i++; i< n){ writeToFlash(addressFlow[i],dataFlow[i]); /* status register polling*/ do{ status_register=readFlash(any_address); /* E or G must be toggled*/ } while (status_register.SR0==1); /* Ready for a new data */ } writeToFlash(another_block_address,FFFFh); /* exit program phase */ /* Exit Phase */ /* status register polling */ do{ status_register=readFlash(any_address); /* E or G must be toggled */ } while (status_register.SR7==0); if (status_register.SR4==1) /*program failure error*/ error_handler(); if (status_register.SR3==1) /*VPP invalid error*/ error_handler(); if (status_register.SR1==1) /*program to protect block error*/ error_handler(); } } 106/114 M58WR064HU M58WR064HL Figure 30. Quadruple Enhanced Factory Program flowchart SETUP PHASE Start Write PD1 Address WA1(1) Flowcharts and pseudo codes LOAD PHASE Write 75h Address WA1 FIRST LOAD PHASE Write PD1 Address WA1 Write PD2 Address WA2(2) Read Status Register Write PD3 Address WA3(2) NO SR7 = 0? YES Write PD4 Address WA4(2) EXIT PHASE Check SR4, SR3 and SR1 for program, VPP and Lock Errors PROGRAM AND VERIFY PHASE Read Status Register Write FFFFh Address = Block WA1 / Exit Check SR4 for Programming Errors NO SR0 = 0? YES Last Page? YES NO End AI06178b 1. Address can remain Starting Address WA1 (in which case the next Page is programmed) or can be any address in the same block. 2. The address is only checked for the first Word of each Page as the order to program the Words is fixed, so subsequent Words in each Page can be written to any address. 107/114 Flowcharts and pseudo codes M58WR064HU M58WR064HL 16.2 Quadruple Enhanced Factory Program pseudo code quad_efp_command(addressFlow,dataFlow,n) /* n is the number of pages to be programmed.*/ { /* Setup phase */ writeToFlash(addressFlow[0],0x75); for (i=0; i++; i< n){ /*Data Load Phase*/ /*First Data*/ writeToFlash(addressFlow[i],dataFlow[i,0]); /*at the first data of the first page, Quad-EFP may be aborted*/ if (First_Page) { status_register=readFlash(any_address); if (status_register.SR7==1){ /*EFP aborted for an error*/ if (status_register.SR4==1) /*program error*/ error_handler(); if (status_register.SR3==1) /*VPP invalid error*/ error_handler(); if (status_register.SR1==1) /*program to protect block error*/ error_handler(); } } /*2nd data*/ writeToFlash(addressFlow[i],dataFlow[i,1]); /*3rd data*/ writeToFlash(addressFlow[i],dataFlow[i,2]); /*4th data*/ writeToFlash(addressFlow[i],dataFlow[i,3]); /* Program&Verify Phase */ do{ status_register=readFlash(any_address); /* E or G must be toggled*/ }while (status_register.SR0==1) } /* Exit Phase */ writeToFlash(another_block_address,FFFFh); /* status register polling */ do{ status_register=readFlash(any_address); /* E or G must be toggled */ } while (status_register.SR7==0); if (status_register.SR1==1) /*program to protected block error*/ error_handler(); if (status_register.SR3==1) /*VPP invalid error*/ error_handler(); if (status_register.SR4==1) /*program failure error*/ error_handler(); } } 108/114 M58WR064HU M58WR064HL Command interface state tables Appendix D Table 42. Command interface state tables Command interface states - modify table, next state Command Input(1) Block Erase, DWP, WP EFP Bank QWP Setup setup(3)(4) Setup(3)(4) Erase (10/40h) (35h, 56h) Setup(3)(4) (30h) (20h, 80h Program Setup Program Setup Erase Setup EFP Setup Erase Read Confirm Program/ Read Clear Electronic P/E Resume, Erase Status status signature, Block Unlock Suspend Register Register Read CFI confirm, EFP (5) (50h) Query (B0h) (70h) Confirm (90h, 98h) (D0h) Ready Ready Ready (Lock Error) Current CI State Read Array(2) (FFh) QuadEFP Setup (75h) Ready Lock/CR Setup Setup OTP Busy Setup Program Busy Suspend Setup Busy Ready QuadEFP Setup Ready (Lock Error) OTP Busy Program Busy Program Busy Program Suspended Ready (error) Erase Busy Erase Suspended Program in Erase Suspend Program Busy Erase Busy Erase Suspended Erase Busy Program Suspended Program Busy Program Suspended Ready (error) Erase Busy Erase Suspend Setup Erase Suspended Erase Suspended Program Busy in Erase Suspend Program Suspend in Program Busy in Erase Suspend Erase Suspend Program Busy in Erase Suspend Erase Suspend EFP Busy EFP Busy(6) EFP Verify(6) Quad EFP Busy(6) Quad EFP Busy(6) Program Suspend in Erase Suspend Program in Erase Suspend Busy Program Busy in Erase Suspend Suspend Lock/CR Setup in Erase Suspend Setup EFP Busy Verify Quad EFP 1. 2. 3. 4. 5. 6. Setup Busy Program Suspend in Erase Suspend Erase Suspend (Lock Error) Ready (error) Erase Suspend (Lock Error) Ready (error) CI = Command Interface, CR = Configuration Register, EFP = Enhanced Factory Program, Quad EFP = Quadruple Enhanced Factory Program, DWP = Double Word Program, QWP = Quadruple Word Program, P/E. C. = Program/Erase Controller. At Power-Up, all banks are in Read Array mode. A Read Array command issued to a busy bank, results in undetermined data output. The two cycle command should be issued to the same bank address. If the P/E.C. is active, both cycles are ignored. The Clear Status Register command clears the Status Register error bits except when the P/E.C. is busy or suspended. EFP and Quad EFP are allowed only when Status Register bit SR0 is set to `0'.EFP and Quad EFP are busy if Block Address is first EFP Address. Any other commands are treated as data. 109/114 Command interface state tables Table 43. Command interface states - modify table, next output(1) Command Input (2) Block DWP, WP EFP Erase, Read QWP (3) (4)(5) Bank Erase Setup Array Setup Setup(4)(5) (4)(5) (FFh) (30h) (10/40h) (35h, 56h) Setup (20h, 80h) M58WR064HU M58WR064HL Current CI State Read Erase Confirm Electronic Quad- P/E Resume, Program/ Read Clear status signature, EFP Block Unlock Erase Status Register(6) Read CFI Setup confirm, EFP Suspend Register (50h) Query Confirm (75h) (B0h) (70h) (90h, 98h) (D0h) Program Setup Erase Setup OTP Setup Program in Erase Suspend EFP Setup EFP Busy EFP Verify Quad EFP Setup Quad EFP Busy Lock/CR Setup Lock/CR Setup in Erase Suspend OTP Busy Ready Program Busy Erase Busy Program/Erase Program Busy in Erase Suspend Program Suspend in Erase Suspend Status Output Register Unchanged Status Register Status Register Array Status Register Output Unchanged Electronic Signature/C FI 1. CI = Command Interface, CR = Configuration Register, EFP = Enhanced Factory Program, Quad EFP = Quadruple Enhanced Factory Program, DWP = Double Word Program, QWP = Quadruple Word Program, P/E. C. = Program/Erase Controller. 2. The output state shows the type of data that appears at the outputs if the bank address is the same as the command address. A bank can be placed in Read Array, Read Status Register, Read Electronic Signature or Read CFI Query mode, depending on the command issued. Each bank remains in its last output state until a new command is issued. The next state does not depend on the bank's output state. 3. At Power-Up, all banks are in Read Array mode. A Read Array command issued to a busy bank, results in undetermined data output. 4. The two cycle command should be issued to the same bank address. 5. If the P/E.C. is active, both cycles are ignored. 6. The Clear Status Register command clears the Status Register error bits except when the P/E.C. is busy or suspended. 110/114 M58WR064HU M58WR064HL Table 44. Command interface states - lock table, next state(1) Command Input Current CI State Lock/CR Setup(2) (60h) Lock/CR Setup OTP Setup(2) (C0h) Block Lock Confirm (01h) Block LockDown Confirm (2Fh) Command interface state tables Set CR Confirm (03h) EFP Exit, Quad EFP Exit(3) Illegal Command (4) P/E. C. Operation Completed Ready Lock/CR Setup Setup OTP Busy Setup Program Busy Suspend Setup Busy Erase Suspend OTP Setup Ready Ready Ready (Lock error) N/A N/A N/A Ready (Lock error) OTP Busy Ready Program Busy Program Busy Program Suspended Ready (error) Erase Busy Lock/CR Setup in Erase Suspend N/A Ready N/A N/A Ready Erase Suspended N/A Setup Program in Erase Suspend Busy Suspend Lock/CR Setup in Erase Suspend Setup EFP Busy Verify Setup QuadEFP Busy Program Busy in Erase Suspend Program Busy in Erase Suspend Program Suspend in Erase Suspend N/A Erase Suspended N/A Erase Suspend (Lock error) Erase Suspend Erase Suspend (Lock error) N/A Ready (error) EFP Busy(5) EFP Verify(5) Quad EFP Busy(5) Quad EFP Busy(5) Ready Quad EFP Busy(5) EFP Verify Ready EFP Busy(5) EFP Verify(5) N/A N/A Ready N/A Ready 1. CI = Command Interface, CR = Configuration Register, EFP = Enhanced Factory Program, Quad EFP = Quadruple Enhanced Factory Program, P/E. C. = Program/Erase Controller. 2. If the P/E.C. is active, both cycles are ignored. 3. EFP and Quad EFP exit when Block Address is different from first Block Address and data is FFFFh. 4. Illegal commands are those not defined in the command set. 5. EFP and Quad EFP are allowed only when Status Register bit SR0 is set to `0'. EFP and Quad EFP are busy if Block Address is first EFP Address. Any other commands are treated as data. 111/114 Command interface state tables Table 45. Command interface states - lock table, next output(1) Command Input Current CI State Block Lock-Down Confirm (2Fh) M58WR064HU M58WR064HL Lock/CR Setup(2) (60h) OTP Setup(2) (C0h) Block Lock Confirm (01h) Set CR Confirm (03h) EFP Exit, Quad EFP Exit(3) Illegal Command(4) P/E. C. Operation Completed Program Setup Erase Setup OTP Setup Program in Erase Suspend EFP Setup EFP Busy EFP Verify Quad EFP Setup Quad EFP Busy Lock/CR Setup Lock/CR Setup in Erase Suspend OTP Busy Ready Program Busy EraseBusy Status Register Program/Erase Program Busy in Erase Suspend Program Suspend in Erase Suspend Output Unchanged Array Status Register Array Status Register Output Unchanged Status Register Output Unchanged 1. CI = Command Interface, CR = Configuration Register, EFP = Enhanced Factory Program, Quad EFP = Quadruple Enhanced Factory Program, P/E. C. = Program/Erase Controller. 2. If the P/E.C. is active, both cycles are ignored. 3. EFP and Quad EFP exit when Block Address is different from first Block Address and data is FFFFh. 4. Illegal commands are those not defined in the command set. 112/114 M58WR064HU M58WR064HL Revision history 17 Revision history Table 46. Date 15-Oct-2004 Document revision history Revision 0.1 First Issue. Table 14: Dual operation limitations added. tWHQV removed throughout document. 80ns speed class removed. X-latency setting clarified. Bank Erase moved to Factory Program command sections. Test conditions modified in DC and AC parameters. Programming command clarified in Command interface - Factory program commands. Table 9: X-Latency Settings, Table 23: Synchronous read AC characteristics and Table 31., M58WR128HU - Parameter Bank Block Addresses corrected. M58WR128HU and M58WR128HL removed, M58WR032HU and M58WR32HL added. VFBGA44 7.5 x 5mm package added. Appendix A: Block address tables revised. All packages are ECOPACK(R). Document promoted from Target specification to full datasheet status. Missing Tables (Table 3, Table 32 and Table 33) and Figure 4 added back. M58WR032HU and M58WR32HL part numbers removed. Small text changes. Removed VFBGA44, 7.5 x 5mm package. VFBGA44 7.5 x 5 package added back (see Section 15: Package mechanical). Small text changes. Daisy chain ordering scheme table removed. Applied Numonyx branding. Changes 31-May-2005 0.2 05-July-2005 0.3 15-Nov-2005 1 18-Nov-2005 18-Apr-2006 2 3 04-May-2006 12-Nov-2007 4 5 113/114 M58WR064HU M58WR064HL Please Read Carefully: INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH NUMONYXTM PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN NUMONYX'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, NUMONYX ASSUMES NO LIABILITY WHATSOEVER, AND NUMONYX DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Numonyx products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications. Numonyx may make changes to specifications and product descriptions at any time, without notice. Numonyx, B.V. may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the presented subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied, by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Numonyx reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. Contact your local Numonyx sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an order number and are referenced in this document, or other Numonyx literature may be obtained by visiting Numonyx's website at http://www.numonyx.com. Numonyx StrataFlash is a trademark or registered trademark of Numonyx or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. Copyright (c) 11/5/7, Numonyx, B.V., All Rights Reserved. 114/114 |
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